Courses · Video series
Lab-paced video lessons you can code along to.
Each lesson ends with a working artifact — RTL, testbench, regression scripts — that you can fork directly into your repo.
6h · 14 lessons
Beginner Series
RTL Foundations
Modeling, simulation intent, lint discipline, and the structure of synthesizable Verilog.
Watch the series 11h · 22 lessons
Intermediate Series
SystemVerilog for Verification
Classes, randomization, assertions, coverage — the language modern DV is written in.
Watch the series 9h · 18 lessons
Intermediate Series
UVM From Zero
Agent, sequencer, driver, monitor, scoreboard — the reusable VIP shape, end to end.
Watch the series 5h · 10 lessons
Advanced Series
AMBA AXI Deep Dive
Channels, handshakes, ordering rules, outstanding transactions, exclusive access.
Watch the series 7h · 12 lessons
Advanced Series
PCIe Verification
TLPs, DLLPs, LTSSM, and the test plan structure for an endpoint or root complex.
Watch the series 5h · 9 lessons
Advanced Series
DDR Bring-Up
Bank groups, training, refresh, and the timing margins that decide whether your SoC boots.
Watch the series