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SystemVerilog tutorials.

The most comprehensive SystemVerilog tutorial — from first principles to advanced verification.

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SystemVerilog Tutorials

The world's most comprehensive SystemVerilog tutorial. 130 pages across 17 modules.

Module 1

Foundations

  1. 01
    What is SystemVerilog?What SystemVerilog is, why it was created, its history, and its critical role in modern chip design and verification.
  2. 02
    SystemVerilog vs VerilogDeep technical comparison — data types, always blocks, interfaces, OOP, assertions, packages.
  3. 03
    Tool SetupQuestaSim, VCS, Xcelium, Verilator, EDA Playground, VS Code, GTKWave — install and first run.
  4. 04
    Your First SystemVerilog ProgramBuild your first SV program from scratch — module anatomy, ports, initial blocks, testbench structure.
Module 2

Data Types

  1. 01
    4-State vs 2-State Typeslogic, bit, reg, wire — X/Z propagation, simulation behavior, synthesis implications.
  2. 02
    Integer Typesbyte, shortint, int, longint, integer, time — signed behavior, overflow, 2-state vs 4-state.
  3. 03
    Real & Shortreal TypesIEEE 754, precision, epsilon comparison, $realtobits, timing calculations.
  4. 04
    String Type & Methodslen, substr, toupper, compare, atoi, itoa, $sformatf — message generation patterns.
  5. 05
    User-Defined Types with typedefNamed aliases, parameterized types, forward declarations, package-level typedefs.
  6. 06
    Enumeration TypesFSM state encoding, enum methods, $cast, waveform naming, unique case.
  7. 07
    Structures — Packed & UnpackedRegister field modeling, protocol frame packing, struct literals.
  8. 08
    Unions & Tagged UnionsPacked unions, overlapping bit fields, tagged union type safety, protocol packet decoding.
  9. 09
    Type Casting & ConversionStatic cast, $signed, $unsigned, $cast, implicit conversions, width truncation.
Module 3

Arrays

  1. 01
    Fixed-Size ArraysPacked vs unpacked, multi-dimensional, initialization, foreach, system functions.
  2. 02
    Dynamic ArraysRuntime sizing with new[], delete(), resize, copy semantics, constraints.
  3. 03
    Associative ArraysArbitrary key types, exists(), delete(), iteration, sparse memory, scoreboard lookup.
  4. 04
    Queuespush/pop, bounded queues, slicing, insert/delete, FIFO modeling.
  5. 05
    Array Methodssort, rsort, find, find_index, sum, min, max, unique — with-clause expressions.
Module 4

Operators & Expressions

  1. 01
    Arithmetic OperatorsPre/post increment & decrement, X-propagation, signed vs unsigned.
  2. 02
    Relational & Equality Operators== vs === with X/Z values, the scoreboard false-pass bug, signed vs unsigned.
  3. 03
    Logical Operators&&, ||, ! — short-circuit evaluation, X propagation, common confusion with bitwise.
  4. 04
    Bitwise Operators&, |, ^, ~, ~^ — masking, bit manipulation, XOR parity, X propagation.
  5. 05
    Reduction Operators&, |, ^, ~&, ~|, ~^ — parity generation, one-hot checking, X propagation.
  6. 06
    Shift Operators<<, >>, <<<, >>> — logical vs arithmetic right shift, signed behavior, sign extension.
  7. 07
    Concatenation, Replication & Conditional{}, {N{}}, ?: — bus assembly, field packing, X-merge behavior.
  8. 08
    Inside OperatorSet membership testing, ranges, arrays, X/Z wildcard behavior, constraint usage.
  9. 09
    Wildcard Equality — ==? and !=?X/Z don't-care matching, mask-based pattern matching, comparison with casex/casez.
  10. 10
    Operator PrecedenceComplete precedence table, associativity rules, classic precedence traps.
Module 5

Procedural Statements

  1. 01
    Procedural Blocksinitial, always, always_comb, always_ff, always_latch — what hardware each one infers.
  2. 02
    if-else & Unique/Priority ModifiersHardware inferred, simulation checks, coverage and synthesis safety.
  3. 03
    case, casex, casez, unique, priorityHardware inference, don't-care matching, modifier safety.
  4. 04
    Loopsfor, while, do-while, repeat, forever, foreach — synthesisable vs simulation-only.
  5. 05
    break, continue, return, disableLoop control — synthesis vs simulation behavior.
  6. 06
    Blocking vs Non-Blocking Assignments= vs <=, the NBA scheduler, the golden rule, race conditions.