Real & Shortreal Types

// ── Declarations ─────────────────────────────────────────────────
real      freq_ghz   = 2.4;      // 64-bit double — initializes to 0.0 if not set
real      voltage    = 1.8;      // VDD
real      pi         = 3.14159265358979;
shortreal approx     = 3.14159;  // 32-bit float — less precision
 
// ── Arithmetic: all standard operators ───────────────────────────
real period_ns = 1.0 / freq_ghz;   // 0.41667 ns
real half_vdd  = voltage / 2.0;    // 0.9 V
 
// ── Math functions (built-in) ─────────────────────────────────────
$sqrt(2.0)               // 1.41421356...
$pow(2.0, 10.0)          // 1024.0
$log(10.0)              // natural log: 2.302585...
$exp(1.0)               // e^1 = 2.71828...
$abs(-3.14)             // 3.14
$floor(3.7)             // 3.0
$ceil(3.2)              // 4.0
$sin(0.0)               // 0.0 (radians)
$cos(0.0)               // 1.0
 
// ── Conversions between real and integer ─────────────────────────
real   r = 3.9;
int    i = int'(r);          // truncate: i = 3 (not rounded)
int    j = int'($round(r));  // rounded:  j = 4
real   back = real'(i);      // int → real: 3.0
 
// ── Bit-level access — for passing real through logic ports ───────
logic [63:0] bits;
real         val = 1.5;
bits = $realtobits(val);             // real → 64-bit pattern
val  = $bitstoreal(bits);             // 64-bit pattern → real
 
logic [31:0] sbits;
shortreal    sval = 1.5;
sbits = $shortrealtobits(sval);       // shortreal → 32-bit
sval  = $bitstoshortreal(sbits);       // 32-bit → shortreal
 
// ── CORRECT comparison: epsilon-based ─────────────────────────────
parameter real EPSILON = 1e-9;
function automatic bit real_eq(real a, b, real eps = EPSILON);
return ($abs(a - b) < eps);
endfunction

module tb_real_basics;
 
real      r    = 0.0;
shortreal sr   = 0.0;
int       i;
 
initial begin
 
// ── Basic arithmetic ──────────────────────────────────────────
r = 2.4e9;              // 2.4 GHz in Hz
$display("Freq: %0.3e Hz", r);
 
real period_ns = 1.0e9 / r;   // period in ns
$display("Period: %0.6f ns", period_ns);   // 0.416667 ns
 
// ── Math functions ────────────────────────────────────────────
$display("sqrt(2) = %0.10f", $sqrt(2.0));     // 1.4142135624
$display("2^10    = %0.0f",  $pow(2.0, 10.0));  // 1024
$display("abs(-5) = %0.1f",  $abs(-5.0));      // 5.0
 
// ── int → real conversion ─────────────────────────────────────
i = 7;
r = real'(i);
$display("int 7 → real: %0.1f", r);    // 7.0
 
// ── real → int: truncates, does NOT round ─────────────────────
r = 3.9;
i = int'(r);
$display("real 3.9 → int (truncate): %0d", i);   // 3 (not 4!)
i = int'($round(r));
$display("real 3.9 → int (round):    %0d", i);   // 4
 
// ── real vs shortreal precision ───────────────────────────────
real      pi_d = 3.14159265358979;
shortreal pi_f = 3.14159265358979;
$display("real      pi: %0.15f", pi_d);   // 3.141592653589790
$display("shortreal pi: %0.15f", pi_f);   // 3.141592741012573 (precision loss)
 
$finish;
end
 
endmodule

Freq: 2.400e+09 Hz
Period: 0.416667 ns
sqrt(2) = 1.4142135624
2^10    = 1024
abs(-5) = 5.0
int 7 → real: 7.0
real 3.9 → int (truncate): 3
real 3.9 → int (round):    4
real      pi: 3.141592653589790
shortreal pi: 3.141592741012573

module tb_timing_check;
 
parameter real CLK_FREQ_GHZ  = 1.0;    // 1 GHz clock
parameter real CLK_PERIOD_NS = 1.0 / CLK_FREQ_GHZ;  // 1.0 ns
parameter real SETUP_TIME_NS = 0.18;   // setup time requirement
parameter real HOLD_TIME_NS  = 0.05;   // hold time requirement
parameter real EPSILON       = 1e-9;   // comparison tolerance
 
real data_arrival_ns;
real clk_edge_ns;
real slack_ns;
 
function automatic bit check_setup(real data_t, clk_t);
real arrival_before_clk = clk_t - data_t;
if (arrival_before_clk < SETUP_TIME_NS - EPSILON) begin
$error("SETUP VIOLATION: data arrives %.3fns before clk, need %.3fns",
arrival_before_clk, SETUP_TIME_NS);
return 0;
end
return 1;
endfunction
 
function automatic bit check_hold(real data_t, clk_t);
real data_after_clk = data_t - clk_t;
if (data_after_clk < HOLD_TIME_NS - EPSILON) begin
$error("HOLD VIOLATION: data changes %.3fns after clk, need %.3fns",
data_after_clk, HOLD_TIME_NS);
return 0;
end
return 1;
endfunction
 
initial begin
clk_edge_ns = 10.0;   // clock edge at 10 ns
 
// Test 1: data arrives 0.25 ns before clock — passes setup (need 0.18)
data_arrival_ns = clk_edge_ns - 0.25;
$display("Test1 setup: %0s", check_setup(data_arrival_ns, clk_edge_ns) ? "PASS" : "FAIL");
 
// Test 2: data arrives 0.10 ns before clock — FAILS setup (need 0.18)
data_arrival_ns = clk_edge_ns - 0.10;
$display("Test2 setup: %0s", check_setup(data_arrival_ns, clk_edge_ns) ? "PASS" : "FAIL");
 
// Test 3: data changes 0.08 ns after clock — passes hold (need 0.05)
real data_change_ns = clk_edge_ns + 0.08;
$display("Test3 hold:  %0s", check_hold(data_change_ns, clk_edge_ns) ? "PASS" : "FAIL");
 
$finish;
end
 
endmodule

module tb_coverage_metrics;
 
int  total_bins     = 256;
int  covered_bins   = 0;
int  hit_counts [256];
real coverage_pct;
real entropy;           // Shannon entropy: measure of distribution uniformity
 
initial begin
// Simulate some bins being hit
foreach (hit_counts[i])
hit_counts[i] = (i < 200) ? (i % 5 + 1) : 0;   // 200 bins covered
 
// Count covered bins
covered_bins = hit_counts.sum() with (item > 0);
 
// Coverage percentage: real division needed for precision
coverage_pct = (real'(covered_bins) / real'(total_bins)) * 100.0;
$display("Coverage: %0.2f%% (%0d/%0d bins)",
coverage_pct, covered_bins, total_bins);
 
// Compute total hits for probability calculation
int  total_hits = hit_counts.sum();
real p;
entropy = 0.0;
 
// Shannon entropy: H = -sum(p * log2(p)) for non-zero bins
foreach (hit_counts[i]) begin
if (hit_counts[i] > 0) begin
p = real'(hit_counts[i]) / real'(total_hits);
entropy += -p * ($log(p) / $log(2.0));  // log2(p)
end
end
$display("Entropy: %0.4f bits (max=%.4f for uniform)",
entropy, $log(real'(covered_bins)) / $log(2.0));
 
$finish;
end
 
endmodule

module tb_real_corners;
 
parameter real EPS = 1e-9;
 
initial begin
 
// ── The equality trap ─────────────────────────────────────────
real a = 0.1 + 0.2;
real b = 0.3;
 
if (a == b)
$display("== : EQUAL");
else
$display("== : NOT EQUAL (a=%.20f, b=%.20f)", a, b);
// Prints: NOT EQUAL — 0.1+0.2 ≠ 0.3 in binary float
 
if ($abs(a - b) < EPS)
$display("epsilon: EFFECTIVELY EQUAL");  // prints
 
// ── $realtobits — pass real through logic interface ───────────
real          send_val = 3.14159;
logic [63:0]   raw_bits;
real          recv_val;
 
raw_bits = $realtobits(send_val);
recv_val = $bitstoreal(raw_bits);
$display("Send: %.10f  Bits: %h  Recv: %.10f",
send_val, raw_bits, recv_val);
// send and recv will be identical (lossless round-trip)
 
// ── Special float values ──────────────────────────────────────
real pos_inf = 1.0 / 0.0;    // +Infinity (tool-dependent — may warn)
real nan_val = 0.0 / 0.0;    // NaN (Not a Number)
$display("1/0 = %f", pos_inf);   // inf
$display("0/0 = %f", nan_val);   // nan
// NaN comparisons: nan == nan → FALSE (always!)
$display("nan == nan: %0b", nan_val == nan_val);  // 0 — NaN never equals itself
 
// ── int cast truncates, not rounds ────────────────────────────
$display("int'(3.9)  = %0d", int'(3.9));   // 3
$display("int'(-3.9) = %0d", int'(-3.9));  // -3 (toward zero)
$display("int'(3.1)  = %0d", int'(3.1));   // 3
 
$finish;
end
 
endmodule

// ── 1. PARAMETERIZED CLOCK TIMING ─────────────────────────────────
parameter real CLK_FREQ_GHZ  = 1.2;
parameter real CLK_HALF_NS   = 1000.0 / (2.0 * CLK_FREQ_GHZ * 1000.0);
// CLK_HALF_NS = 0.4167 ns — use with timeprecision 1ps
 
// ── 2. VOLTAGE THRESHOLD CHECK ────────────────────────────────────
real vdd_nominal = 1.8;
real margin      = 0.1;    // ±10%
real measured_v;
// Check if voltage is within tolerance:
// if ($abs(measured_v - vdd_nominal) > margin)
//   $error("Voltage %.3fV outside tolerance", measured_v);
 
// ── 3. $realtime FOR SUB-NANOSECOND TIMESTAMPS ───────────────────
real t_req, t_resp, latency_ns;
// t_req = $realtime;  // captures fractional ns
// ... wait for response ...
// t_resp = $realtime;
// latency_ns = t_resp - t_req;
 
// ── 4. PASS real THROUGH LOGIC PORT USING $realtobits ─────────────
// Some modules pass real-valued samples through logic vectors:
function automatic logic [63:0] pack_real(real val);
return $realtobits(val);
endfunction
function automatic real unpack_real(logic [63:0] bits);
return $bitstoreal(bits);
endfunction
 
// ── 5. COVERAGE METRICS ───────────────────────────────────────────
real coverage_pct(int covered, total);
return (real'(covered) / real'(total)) * 100.0;
endfunction
// Note: int/int gives 0 for covered<total — always cast to real first
 
// ── 6. AMS VERIFICATION: VAMS / UVM-AMS integration ─────────────
// real used to represent analog output values from mixed-signal DUT:
// real vout_v;   // output voltage from ADC reference model
// real iout_ua;  // output current in microamps

real measured = 0.1 + 0.2;   // = 0.30000000000000004
real expected = 0.3;           // = 0.29999999999999998...
 
// BUGGY: direct == comparison silently fails
if (measured == expected)
$display("PASS");    // NEVER fires even though "logically" equal
else
$error("FAIL");     // always fires — false mismatch
 
// FIXED: epsilon comparison
parameter real EPS = 1e-9;
if ($abs(measured - expected) < EPS)
$display("PASS");    // fires correctly

int  covered = 75;
int  total   = 100;
 
// BUGGY: integer division happens first, then converts to real
real pct_wrong = covered / total * 100.0;
$display("Wrong pct: %0.1f%%", pct_wrong);   // 0.0% — 75/100=0 in int division!
 
// FIXED: cast to real BEFORE dividing
real pct_right = (real'(covered) / real'(total)) * 100.0;
$display("Right pct: %0.1f%%", pct_right);   // 75.0%
 
// Rule: whenever you divide integers and expect a fractional result,
// cast at least one operand to real BEFORE the division

real cycles_per_byte = 1000.0 / 8.0;   // 125.0 — exact
real period_frac     = 1.0 / 3.0;       // 0.333... — repeating
real slack           = 0.9999999999;    // just under 1.0
 
// BUGGY: engineer expects rounding, gets truncation
int periods_needed = int'(slack * 10.0);  // 9.999... → int'() = 9 (not 10)
$display("Periods needed: %0d", periods_needed);  // 9 — expected 10
 
// FIXED: use $round() before casting
int correct = int'($round(slack * 10.0));  // rounds to 10
$display("Correct:         %0d", correct);         // 10
 
// Rule: always think about whether you want truncation or rounding
// int'(x)           → truncate toward zero (floor for positive)
// int'($round(x))   → round to nearest integer
// int'($floor(x))   → floor (round toward -infinity)
// int'($ceil(x))    → ceiling (round toward +infinity)

// BUGGY: real used inside synthesizable RTL
module bad_rtl (input logic [7:0] a, b, output logic [7:0] result);
real temp;
always_comb begin
temp   = real'(a) * 1.5;    // synthesis FAILS — real not supported
result = logic'(temp);
end
endmodule
 
// CORRECT: scale using fixed-point integer arithmetic
module good_rtl (input logic [7:0] a, output logic [8:0] result);
// ×1.5 = ×3/2 = (a + a>>1) — exact fixed-point equivalent
assign result = {1'b0, a} + {1'b0, a[7:1]};  // a + a/2 = a*1.5
endmodule