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VLSIMentor

Verilog

Build a working foundation in Verilog — modeling, simulation, and synthesizable RTL.

Foundation 4h 0m readRTLSimulationSynthesis

This is the foundation course for any aspiring RTL designer or verification engineer. You will learn to write synthesizable Verilog the way it is written in production — not the textbook way.

Who this is for

  • Final-year B.Tech / M.Tech students in ECE, EEE, CSE
  • Working engineers transitioning into VLSI
  • Anyone preparing for RTL design or DV interviews

Prerequisites

  • Basic digital electronics (gates, flip-flops, combinational vs sequential)
  • Comfort with any one programming language

Syllabus

Week 1 — Verilog basics

Lexical conventions, data types, vectors, parameters, simulation vs synthesis.

Week 2 — Combinational logic

assign, always @*, case statements, priority vs parallel, common bugs.

Week 3 — Sequential logic

Flip-flops, latches (and why we avoid them), reset strategies, clock domains.

Week 4 — Finite State Machines

Mealy vs Moore, one-hot vs binary encoding, state-machine refactoring.

Week 5 — Pipelining and timing

Pipeline stages, hazards, retiming, clock-gating awareness.

Week 6 — Memories and arbitration

Single/dual-port RAMs, FIFOs, round-robin and priority arbiters.

Week 7 — Synthesis & coding guidelines

Reading synthesis reports, common coding pitfalls, lint checks.

Week 8 — Capstone project

Design a small IP block (UART, SPI master, or a 4-port arbiter) and run it through a simulation flow.

Sample code

A simple synthesizable 2-state FSM:

module simple_fsm (
  input  logic clk,
  input  logic rst_n,
  input  logic start,
  output logic busy
);
  typedef enum logic [0:0] { IDLE, RUN } state_t;
  state_t state, next_state;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) state <= IDLE;
    else        state <= next_state;
  end
 
  always_comb begin
    next_state = state;
    unique case (state)
      IDLE: if (start)  next_state = RUN;
      RUN : if (!start) next_state = IDLE;
    endcase
  end
 
  assign busy = (state == RUN);
endmodule

What you'll build

  • 4-bit ALU with overflow detection
  • Synchronous FIFO with full/empty flags
  • UART transmitter at configurable baud rate
  • Round-robin arbiter with grant hold

Next steps after this course