Fixed-Size Arrays

// ── PACKED ARRAY (single wide vector) ────────────────────────────
logic [31:0] word;              // 32-bit packed: one contiguous signal
logic [7:0] byte_val;           // 8-bit packed: standard byte
 
// ── UNPACKED ARRAY (N elements, each of given type) ───────────────
logic [7:0] mem    [256];       // 256 elements × 8-bit  (0..255)
logic [7:0] fifo   [0:63];      // 64 elements  × 8-bit  (explicit range)
int           scores [16];       // 16 integers (signed 32-bit each)
 
// ── MULTI-DIMENSIONAL UNPACKED ────────────────────────────────────
logic [7:0] matrix [4][4];      // 4 rows × 4 cols of bytes
logic        bitmask[8][8];      // 8×8 array of single bits
 
// ── PACKED MULTI-DIMENSIONAL ──────────────────────────────────────
logic [3:0][7:0] reg_file;      // one 32-bit signal (4 packed bytes)
// reg_file[3] = bits [31:24], reg_file[0] = bits [7:0]
 
// ── INITIALIZATION AT DECLARATION ────────────────────────────────
int           defaults[4] = '{0, 1, 2, 3};       // array literal
logic [7:0] cleared [4] = '{4{8'h00}};          // all zeros
logic [7:0] preset  [3] = '{8'hAA, 8'hBB, 8'hCC};
 
// ── ACCESS ────────────────────────────────────────────────────────
mem[0]      = 8'hFF;            // write element 0
matrix[2][3] = 8'hAB;           // write row 2, col 3
 
// ── SYSTEM FUNCTIONS ─────────────────────────────────────────────
$size(mem)         // = 256   (total elements in first dimension)
$size(matrix, 1)   // = 4     (size of dimension 1 = rows)
$size(matrix, 2)   // = 4     (size of dimension 2 = cols)
$dimensions(mem)   // = 1     (one unpacked dimension)
$low(fifo)          // = 0     (lowest index)
$high(fifo)         // = 63    (highest index)
$left(mem)          // = 0     (leftmost declared index)
$right(mem)         // = 255   (rightmost declared index)

module tb_array_basics;
 
logic [7:0] data [8];          // 8-element byte array
int           total;
int           i;
 
initial begin
 
// ── Initialize all elements ──────────────────────────────────
foreach (data[i])
data[i] = i * 16;           // 0x00, 0x10, 0x20, ... 0x70
 
// ── Read and display ─────────────────────────────────────────
$display("Array contents:");
foreach (data[i])
$display("  data[%0d] = 0x%02h", i, data[i]);
 
// ── System functions ─────────────────────────────────────────
$display("$size(data)       = %0d", $size(data));        // 8
$display("$low(data)        = %0d", $low(data));         // 0
$display("$high(data)       = %0d", $high(data));        // 7
$display("$dimensions(data) = %0d", $dimensions(data));  // 1
 
// ── Whole-array copy ─────────────────────────────────────────
logic [7:0] copy [8];
copy = data;                   // single statement — copies all 8 elements
$display("copy[3] = 0x%02h  (should be 0x30)", copy[3]);
 
// ── Whole-array comparison ───────────────────────────────────
if (copy == data)
$display("copy and data are identical");
data[0] = 8'hFF;
if (copy != data)
$display("copy and data now differ at [0]");
 
// ── Sum using a loop ─────────────────────────────────────────
total = 0;
foreach (data[i]) total += data[i];
$display("Sum = %0d", total);
 
$finish;
end
 
endmodule

Array contents:
data[0] = 0x00
data[1] = 0x10
data[2] = 0x20
data[3] = 0x30
data[4] = 0x40
data[5] = 0x50
data[6] = 0x60
data[7] = 0x70
$size(data)       = 8
$low(data)        = 0
$high(data)       = 7
$dimensions(data) = 1
copy[3] = 0x30  (should be 0x30)
copy and data are identical
copy and data now differ at [0]
Sum = 376

// Simplified 32-entry, 32-bit register file — common in RISC-V style cores
module reg_file (
input  logic        clk,
input  logic        we,          // write enable
input  logic [4:0]  wr_addr,      // 5-bit = 32 entries
input  logic [31:0] wr_data,
input  logic [4:0]  rd_addr,
output logic [31:0] rd_data
);
 
logic [31:0] regs [0:31];          // 32 × 32-bit static array
 
// Synchronous write
always_ff @(posedge clk)
if (we && wr_addr != 5'b0)       // reg[0] is hardwired to 0 in RISC-V
regs[wr_addr] <= wr_data;
 
// Asynchronous read (combinational)
assign rd_data = (rd_addr == 5'b0) ? 32'h0 : regs[rd_addr];
 
endmodule
 
// Testbench
module tb_reg_file;
logic        clk = 0;
logic        we;
logic [4:0]  wr_addr, rd_addr;
logic [31:0] wr_data, rd_data;
 
reg_file dut(.*);
always #5 clk = ~clk;
 
initial begin
we = 1; wr_addr = 5'd5; wr_data = 32'hCAFE_BABE;
@(posedge clk); #1;
 
we = 0; rd_addr = 5'd5;
#1;
$display("reg[5] = 0x%08h  (expect CAFEBABE)", rd_data);
 
// reg[0] always reads 0
rd_addr = 5'd0; #1;
$display("reg[0] = 0x%08h  (expect 00000000)", rd_data);
$finish;
end
endmodule

module tb_packet_buffer;
 
parameter int MAX_PKT = 8;
parameter int PKT_LEN = 16;    // bytes per packet
 
typedef logic [7:0] byte_t;
typedef byte_t pkt_t [PKT_LEN];  // one packet = 16-byte array
 
pkt_t  send_buf [MAX_PKT];       // buffer of 8 packets
pkt_t  recv_buf [MAX_PKT];       // received copy
int    mismatch_cnt;
int    i, j;
 
// Build expected packets (fill with known pattern)
task automatic build_packets();
foreach (send_buf[i, j])
send_buf[i][j] = (i * PKT_LEN + j) & 8'hFF;
endtask
 
// Simulate DUT output (correct + one injected error)
task automatic simulate_recv();
recv_buf = send_buf;            // whole-array copy
recv_buf[3][7] = 8'hFF;       // inject error: pkt 3, byte 7
endtask
 
// Compare and report
task automatic check_packets();
mismatch_cnt = 0;
foreach (send_buf[i]) begin
if (send_buf[i] != recv_buf[i]) begin   // compare entire packet
foreach (send_buf[i, j]) begin
if (send_buf[i][j] !== recv_buf[i][j]) begin
$error("PKT[%0d][%0d]: exp=0x%02h got=0x%02h",
i, j, send_buf[i][j], recv_buf[i][j]);
mismatch_cnt++;
end
end
end
end
if (mismatch_cnt == 0)
$display("PASS: all %0d packets match", MAX_PKT);
else
$display("FAIL: %0d mismatches detected", mismatch_cnt);
endtask
 
initial begin
build_packets();
simulate_recv();
check_packets();
$finish;
end
 
endmodule

ERROR: PKT[3][7]: exp=0x37 got=0xFF
FAIL: 1 mismatches detected

module tb_corner_cases;
 
logic [7:0] uninitialized [4];   // not initialized — will be X
logic [7:0] packed_access [4];
 
initial begin
 
// ── Uninitialized = X ─────────────────────────────────────────
$display("uninitialized[0] = %02h", uninitialized[0]);  // xx
$display("uninitialized[0] === 8'hxx: %0b",
uninitialized[0] === 8'hxx);               // 1
 
// ── Out-of-bounds: no error, returns X ───────────────────────
logic [7:0] uninitialized [4];
// Accessing index 5 in a 4-element array (valid indices: 0-3)
$display("out-of-bounds [5] = %02h", uninitialized[5]); // xx
// Simulation does NOT throw an error — it just returns X
 
// ── Packed slice on unpacked element ─────────────────────────
packed_access[0] = 8'hAB;
$display("lower nibble: %h", packed_access[0][3:0]);   // B
$display("bit 7:        %b", packed_access[0][7]);     // 1
 
// ── Array literal assignment ──────────────────────────────────
packed_access = '{8'hAA, 8'hBB, 8'hCC, 8'hDD};
$display("[0]=%02h [1]=%02h [2]=%02h [3]=%02h",
packed_access[0], packed_access[1],
packed_access[2], packed_access[3]);
// Note: '{} assigns index 0 first (leftmost = index 0)
 
// ── Default value in literal ──────────────────────────────────
packed_access = '{default: 8'hFF};   // fill all elements with FF
$display("after default fill: [2]=%02h", packed_access[2]); // FF
 
$finish;
end
 
endmodule

uninitialized[0] = xx
uninitialized[0] === 8'hxx: 1
out-of-bounds [5] = xx
lower nibble: b
bit 7:        1
[0]=AA [1]=BB [2]=CC [3]=DD
after default fill: [2]=FF

// ── 1. SCOREBOARD: expected vs received transaction buffer ────────
logic [31:0] exp_data  [16];    // expected DUT output (pre-computed)
logic [31:0] got_data  [16];    // captured DUT output
 
if (got_data !== exp_data)       // whole-array !== catches X mismatches too
$error("Buffer mismatch detected");
 
// ── 2. MONITOR: byte capture buffer for incoming AXI beat ─────────
logic [7:0] beat_bytes [64];    // 64-byte max beat
int           byte_count = 0;
 
// In the monitor's capture loop:
// beat_bytes[byte_count++] = captured_byte;
 
// ── 3. DRIVER: pre-loaded stimulus table ──────────────────────────
logic [31:0] stim_table [256] = '{default: 32'h0};
// Load from file at sim start:
// $readmemh("stim.hex", stim_table);
 
// ── 4. CONSTRAINT: fixed-size array inside rand class ─────────────
class axi_burst_txn;
rand logic [7:0]  data [16];   // 16-byte fixed burst
rand logic [7:0]  strb [16];   // strobe per byte
 
constraint valid_strb {
foreach (strb[i])
strb[i] inside {8'h00, 8'hFF};   // either all-masked or all-valid
}
endclass
 
// ── 5. SVA ASSERTION: check stable array contents ─────────────────
// property p_stable_lut;
//   @(posedge clk) !update_en |=> lut_array == $past(lut_array);
// endproperty
// assert property (p_stable_lut);
 
// ── 6. $readmemh / $writememh for file-based initialization ───────
logic [31:0] rom [1024];
initial
$readmemh("rom_init.hex", rom);  // loads hex values from file into array
// rom_init.hex format: one hex value per line, e.g.:
// CAFEBABE
// 00000001
// ...

logic [31:0] ref_model [64];     // BUGGY: no initialization
 
initial begin
// DUT just completed — compare against reference model
if (dut_output !== ref_model[0])   // ref_model[0] is X — always mismatches!
$error("MISMATCH at [0]");            // fires even when DUT is correct
end
 
// FIXED: initialize before use
logic [31:0] ref_model [64] = '{default: 32'h0};  // all zeros
// OR load from file:
initial $readmemh("expected.hex", ref_model);

logic [7:0] buf [4];
 
// BUGGY: { } is concatenation, not array literal assignment
buf = {8'hAA, 8'hBB, 8'hCC, 8'hDD};  // COMPILE ERROR or type mismatch
// Concatenation produces a packed 32-bit value, not an unpacked array
 
// FIXED: use '{ } for unpacked array literals
buf = '{8'hAA, 8'hBB, 8'hCC, 8'hDD};   // CORRECT: array literal
 
// Also valid for default fill:
buf = '{default: 8'hFF};                  // fills all 4 elements with 0xFF
 
// And for partial init with default:
buf = '{8'h01, 8'h02, default: 8'h00};   // [0]=01, [1]=02, [2]=00, [3]=00

// Module declares an unpacked port
module dut (input logic [7:0] data_in [4]);   // unpacked [4]
// ...
endmodule
 
module tb;
logic [31:0] packed_sig;    // 32-bit packed
logic [7:0] unpack_arr [4]; // 4-element unpacked
 
// BUGGY: connecting a packed 32-bit signal to an unpacked [4][8] port
dut d1 (.data_in(packed_sig));    // TYPE ERROR at elaboration
 
// CORRECT: connect matching unpacked array
dut d2 (.data_in(unpack_arr));    // types match
 
// If you genuinely need to convert between the two, use explicit assignment:
always_comb begin
foreach (unpack_arr[i])
unpack_arr[i] = packed_sig[i*8 +: 8];  // slice bytes from packed sig
end
endmodule

logic [7:0] matrix [4][8];    // [4 rows][8 cols]
 
// BUGGY: engineer wants row 2, column 5 but swaps dimensions
logic [7:0] val = matrix[5][2];  // reads col 5 of row... wait, index 5 on dim[4] is OUT OF BOUNDS
// matrix[5] returns X (out of bounds on first dim which only goes 0..3)
// matrix[5][2] = X — no error, silent wrong result
 
// CORRECT: first index = row (0..3), second = col (0..7)
val = matrix[2][5];             // row 2, column 5
 
// RULE: dimensions are indexed left-to-right as declared
// logic [7:0] matrix [ROWS][COLS]  →  matrix[row][col]