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Learnings · Verilog

Verilog tutorials.

Modeling, simulation, synthesizable Verilog, FSMs, and pipelining — taught the way working RTL teams write it.

Authoring in progress

The Verilog track is being authored to the SystemVerilog standard.

Until the chapters below land, take the SystemVerilog foundations track — every Verilog idiom is covered alongside the modern equivalent.

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Coming up

  1. 01
    Lexical conventions and module structureCompiler directives, modules, ports, and the simulation vs. synthesis split.
  2. 02
    Combinational logic with always @*case vs. priority encoders, default values, common combinational bugs.
  3. 03
    Sequential logic and clockingFlip-flops, latches, reset strategies, and clock-domain hygiene.
  4. 04
    Finite state machinesMealy vs. Moore, encoding styles, hierarchical FSMs, and lint-clean refactors.
  5. 05
    Pipelining and timing intentStage balancing, retiming, hazards, and synthesis hints.
  6. 06
    Memories, FIFOs, and arbitrationSingle/dual-port RAMs, round-robin and priority arbiters, AHB-Lite-style register files.