UVM
Universal Verification Methodology — agents, environments, sequences, and reusable VIP architecture.
Advanced 7h 0m readMethodologyVIPReuse
UVM is the industry-standard methodology for SystemVerilog testbenches. This course takes you from "hello UVM" all the way to a coverage-closed testbench for a real IP block.
Course outline
Weeks 1–2 — UVM foundations
TLM, factory, configuration database, phasing.
Weeks 3–4 — Building a UVM agent
Driver, monitor, sequencer, sequence items. Active vs passive agents.
Week 5 — Sequences and virtual sequences
Layered stimulus, virtual sequencer for multi-agent testbenches.
Week 6 — Scoreboards and coverage
Self-checking testbenches, functional coverage, coverage closure strategy.
Week 7 — Register Abstraction Layer (RAL)
Auto-generated register models, backdoor access, predictor.
Week 8 — Advanced topics
Callbacks, policy classes, end-of-test logic, custom phases.
Weeks 9–10 — Capstone
Verify a real IP — AHB-Lite slave, I²C master, or custom DUT — end-to-end.