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VLSIMentor

PCIe

PCI Express layered architecture, LTSSM, TLPs, DLLPs, and verification considerations.

Expert 5h 0m readSerdesHigh-speed

PCIe is the high-speed serial interconnect that connects CPUs to GPUs, SSDs, NICs, and accelerators. Verifying PCIe is one of the highest-paid skills in the industry.

Layered architecture

  • Physical layer (PHY) — SerDes, 8b/10b or 128b/130b encoding, link training (LTSSM)
  • Data Link Layer (DLL) — ACK/NAK, flow control credits
  • Transaction Layer (TL) — TLPs, configuration, memory reads/writes, completions

What you'll learn

  • Link training and state machines
  • TLP packet formats (memory, IO, config, message)
  • Flow control credits and posted/non-posted transactions
  • Error reporting and recovery
  • Building a PCIe endpoint testbench
  • Gen3 / Gen4 / Gen5 / Gen6 differences