SystemVerilog
OOP, interfaces, randomization, functional coverage, and assertion-based verification.
SystemVerilog is Verilog's superset — adding object-oriented programming, randomization, assertions, and functional coverage. Essential for any modern verification engineer.
Syllabus
Week 1 — New data types
logic, bit, packed/unpacked arrays, structs, enums, typedefs.
Week 2 — Interfaces and modports
Eliminate port-list bloat; encapsulate protocols.
Week 3 — Object-oriented programming
Classes, inheritance, polymorphism, virtual methods.
Week 4 — Randomization
rand, randc, constraints, weighted distributions.
Week 5 — Assertions (SVA)
Immediate and concurrent assertions, properties, sequences.
Week 6 — Functional coverage
covergroup, coverpoints, cross coverage, coverage closure.
Week 7 — Mailboxes, semaphores, events
Inter-process communication for testbench components.
Week 8 — Mini testbench project
Build a class-based testbench (no UVM yet) for a simple DUT.
Next step
After SystemVerilog, UVM is the natural next course.