break, continue, return, disable

// ── Find first set bit (priority encoder) ───────────────────────
always_comb begin
first_set = 4'hF;          // default: no bit found
for (int i = 0; i < 8; i++) begin
if (data[i]) begin
first_set = i[3:0];
break;              // stop as soon as first '1' found
end
end
end
 
// ── Testbench: stop listening once error seen ───────────────────
initial begin
for (int pkt = 0; pkt < 1000; pkt++) begin
@(posedge clk);
if (error_flag) begin
$error("Error at packet %0d", pkt);
break;              // no point sending more after an error
end
drive_packet(pkt);
end
end
 
// ── break in nested loops: only exits the innermost loop ────────
initial begin
for (int r = 0; r < 4; r++) begin      // outer loop continues
for (int c = 0; c < 4; c++) begin
if (c == 2) break;            // exits inner loop at c=2
$display("[%0d][%0d]", r, c);  // prints [r][0] and [r][1] only
end
end
end

// ── Sum only even-indexed elements ──────────────────────────────
always_comb begin
even_sum = '0;
for (int i = 0; i < 8; i++) begin
if (i[0]) continue;     // skip odd indices (i[0]=1 when odd)
even_sum += data[i];
end
end
 
// ── Testbench: log only valid transactions ───────────────────────
initial begin
for (int i = 0; i < 100; i++) begin
@(posedge clk);
if (!valid) continue;    // skip idle cycles
$display("[%0t] data=%0h", $time, data);
end
end
 
// ── continue vs break side-by-side ──────────────────────────────
initial begin
for (int i = 0; i < 5; i++) begin
if (i == 3) continue;    // prints 0,1,2,4  (skips 3)
$display("i = %0d", i);
end
 
for (int i = 0; i < 5; i++) begin
if (i == 3) break;       // prints 0,1,2    (stops at 3)
$display("i = %0d", i);
end
end

// ── return with value in a function ─────────────────────────────
function automatic int clz(input logic [7:0] data);
for (int i = 7; i >= 0; i--)
if (data[i]) return 7 - i;   // count leading zeros from MSB
return 8;                           // all zeros → 8
endfunction
 
// ── return in a task (no value) ─────────────────────────────────
task automatic send_packet(input int size);
if (size <= 0) begin
$warning("send_packet: invalid size %0d, aborting", size);
return;                         // early exit, no further execution
end
for (int b = 0; b < size; b++) begin
@(posedge clk);
data = $random;
valid = 1;
end
valid = 0;
endtask
 
// ── Multiple return paths (guard clauses pattern) ───────────────
function automatic logic [7:0] saturate_add(
input logic [7:0] a, b);
logic [8:0] sum = a + b;
if (sum[8]) return 8'hFF;  // overflow → saturate at max
return sum[7:0];             // normal result
endfunction

// ── disable label: exit a named block ──────────────────────────
initial begin
// label a named block with: begin : label_name
begin : search_block
for (int i = 0; i < 16; i++) begin
if (mem[i] == target) begin
found_idx = i;
disable search_block;   // jump out of the named block
end
end
found_idx = -1;               // not reached if disable fires
end
end
 
// ── disable fork: kill spawned threads ──────────────────────────
initial begin
fork
begin : timeout_proc
#10_000;               // watchdog: 10 000 time units
$fatal("TIMEOUT");
end
begin : main_proc
run_test();             // actual test sequence
end
join_any
disable fork;               // kill whichever thread didn't finish
end
 
// ── disable task (kills an executing named task) ────────────────
task automatic long_driver();
for (int i = 0; i < 1000; i++) begin
@(posedge clk);
data = i;
end
endtask
 
initial begin
fork
long_driver();
join_none
#200;
disable long_driver;        // abort task after 200 time units
end

// ── break in for loop — synthesis perspective ─────────────────────
always_comb begin
first = 4'hF; // default
for (int i = 0; i < 8; i++) begin
if (data[i]) begin
first = i[3:0];
break;          // stop at first '1'
end
end
end
 
// ── Synthesis unrolls to equivalent hardware (NO break in netlist):
always_comb begin
logic found;
first = 4'hF; found = 0;
if (!found && data[0]) begin first = 0; found = 1; end  // i=0
if (!found && data[1]) begin first = 1; found = 1; end  // i=1
if (!found && data[2]) begin first = 2; found = 1; end  // i=2
// ... and so on for all 8 iterations
// Hardware: cascade of AND gates checking !found — priority encoder
end
 
// ── continue in for loop — synthesis perspective ──────────────────
always_comb begin
even_sum = '0;
for (int i = 0; i < 8; i++) begin
if (i[0]) continue;  // skip odd
even_sum += data[i];
end
end
 
// ── Synthesis unrolls to (hardware identical):
always_comb begin
even_sum = '0;
if (!1'b0) even_sum += data[0];   // i=0: i[0]=0, not skipped
// if (!1'b1) → constant false → data[1] never added (optimized away)
if (!1'b0) even_sum += data[2];   // i=2: i[0]=0, not skipped
// ... pattern continues
// Hardware: adder with 4 inputs (data[0,2,4,6]). No gates for odd indices.
end

// ── Pattern 1: Priority encoder with break ────────────────────────
module prio_enc #(parameter int N = 8) (
input  logic [N-1:0]     req,
output logic [$clog2(N):0] grant_id,
output logic              valid
);
always_comb begin
grant_id = '0;
valid    = 1'b0;
for (int i = 0; i < N; i++) begin
if (req[i]) begin
grant_id = i[$clog2(N):0];
valid    = 1'b1;
break;           // req[0] is highest priority — stop here
end
end
end
endmodule
// break here: synthesis generates a standard priority encoder tree
// Equivalent to priority if chain — break makes the code read naturally
 
// ── Pattern 2: Checksum over valid bytes (continue skips invalid) ─
module valid_checksum (
input  logic [7:0] data [16],
input  logic        valid [16],  // per-byte valid mask
output logic [7:0] checksum
);
always_comb begin
checksum = 8'h00;
for (int i = 0; i < 16; i++) begin
if (!valid[i]) continue;   // skip invalid bytes
checksum ^= data[i];          // XOR only valid bytes
end
end
endmodule
// continue: synthesis generates 16 AND gates (valid[i] & data[i])
// feeding an XOR tree. Invalid bytes produce 0 contribution → correct
 
// ── Pattern 3: Memory search with break (find match in TCAM style) ─
module cam_lookup #(parameter int DEPTH=16, WIDTH=8) (
input  logic [WIDTH-1:0] key,
input  logic [WIDTH-1:0] mem [DEPTH],
output logic [$clog2(DEPTH):0] match_addr,
output logic               hit
);
always_comb begin
match_addr = '0;
hit        = 1'b0;
for (int i = 0; i < DEPTH; i++) begin
if (mem[i] == key) begin
match_addr = i[$clog2(DEPTH):0];
hit        = 1'b1;
break;         // return lowest-address match
end
end
end
endmodule

// ── Saturating arithmetic with multiple return paths ──────────────
function automatic logic [7:0] sat_add8(
input logic [7:0] a, b);
logic [8:0] wide = a + b;
if (wide[8]) return 8'hFF;    // overflow → saturate max
return wide[7:0];              // normal
endfunction
// Synthesis: 9-bit adder → 2:1 mux on bit[8] → saturate or pass
 
// ── Priority encode with guard and early return ──────────────────
function automatic logic [2:0] penc3(
input logic [7:0] req);
if (req == 8'h00) return 3'd7;  // no request → sentinel value
for (int i = 0; i < 8; i++)
if (req[i]) return i[2:0];  // first set bit → priority encode
return 3'd7;                       // unreachable but satisfies tool
endfunction
// Guard clause (req==0 check) is synthesized as a separate 8-input NOR
// feeding a 2:1 mux that selects between sentinel and the encoder output
 
// ── AXI response handler with error guard ────────────────────────
function automatic logic [7:0] decode_axi_resp(
input logic [1:0] resp,
input logic        valid);
if (!valid)            return 8'hFF;  // guard: not valid
if (resp == 2'b10)    return 8'hFE;  // SLVERR
if (resp == 2'b11)    return 8'hFD;  // DECERR
return 8'h00;                         // OKAY/EXOKAY
endfunction

// ── Pattern 1: Timeout watchdog using fork-join_any + disable fork
module tb_with_watchdog;
initial begin
fork
begin : test_body
run_directed_test();   // main stimulus
run_random_test();
end
begin : watchdog
#1_000_000;           // timeout: 1M time units
$fatal(1, "WATCHDOG: test timed out");
end
join_any
disable fork;             // kill whichever thread is still running
// Control resumes here after EITHER test_body OR watchdog finishes
$display("Test complete at t=%0t", $time);
$finish;
end
endmodule
 
// ── Pattern 2: Coverage-driven test with disable label ────────────
initial begin
begin : coverage_test
int max_cycles = 100_000;
for (int cycle = 0; cycle < max_cycles; cycle++) begin
@(posedge clk);
drive_random_stimulus();
if (coverage_goal_met()) begin
$display("Coverage goal met at cycle %0d", cycle);
disable coverage_test;   // exit the named block early
end
end
$display("Coverage NOT met after %0d cycles", max_cycles);
end
end
 
// ── Pattern 3: Protocol handshake with configurable timeout ───────
task automatic wait_for_handshake(
input int timeout_cycles,
output bit timed_out
);
timed_out = 0;
fork
begin : hs_wait
@(posedge clk iff (valid && ready));  // wait for handshake
end
begin : hs_timeout
repeat(timeout_cycles) @(posedge clk);
timed_out = 1;
end
join_any
disable fork;   // clean up whichever thread is still waiting
if (timed_out) $error("Handshake timeout after %0d cycles", timeout_cycles);
endtask

module tb_complete;
logic clk = 0, rst_n;
logic [7:0] data_in, data_out;
logic       valid, ready, error_flag;
int         pass_cnt=0, fail_cnt=0, tx_cnt=0;
 
// ── Clock ─────────────────────────────────────────────────────
initial forever #5 clk = ~clk;
 
// ── Reset ─────────────────────────────────────────────────────
initial begin
rst_n = 0;
repeat(4) @(posedge clk);
rst_n = 1;
end
 
// ── Stimulus driver using break and continue ──────────────────
task automatic drive_stimulus();
@(posedge rst_n);
for (int i = 0; i < 1000; i++) begin
@(posedge clk);
if (error_flag) begin
$error("Error at i=%0d — stopping stimulus", i);
break;               // stop on first error
end
if (!ready) continue;   // skip when DUT not ready
data_in = $urandom;
valid   = 1'b1;
tx_cnt++;
end
valid = 1'b0;
endtask
 
// ── AXI response handler using return guard ───────────────────
task automatic check_output();
@(posedge clk);
if (!valid)   return;        // guard: not a valid transaction
if (error_flag) return;       // guard: DUT in error state
if (data_out === ~data_in) pass_cnt++;
else begin
$error("got %h exp %h", data_out, ~data_in);
fail_cnt++;
end
endtask
 
// ── Main test with timeout watchdog using disable fork ────────
initial begin
fork
begin : test_main
drive_stimulus();
$display("Done: tx=%0d pass=%0d fail=%0d",tx_cnt,pass_cnt,fail_cnt);
end
begin : watchdog
#500_000;
$fatal(1, "WATCHDOG timeout");
end
join_any
disable fork;
$finish;
end
 
// ── Monitor (uses continue to skip non-valid cycles) ─────────
initial forever begin
@(posedge clk);
if (!valid) continue;      // wait for valid — skip idle
check_output();
end
endmodule

// ❌ BUG: engineer intended to stop logging on error, but break exits forever
initial begin
forever begin
@(posedge clk);
if (valid) $display("[%0t] data=%h", $time, data_out);
if (error_flag) begin
$error("Error detected");
break;   // ❌ exits the forever loop entirely!
// Monitor STOPS. Error reported at T=X,
// but subsequent transactions NEVER checked.
// Test appears to pass — missing error detections.
end
end
end
 
// ✅ FIX 1: Don't break from monitor — just flag the error and continue
initial begin
forever begin
@(posedge clk);
if (valid) $display("[%0t] data=%h", $time, data_out);
if (error_flag) $error("Error detected");  // continue monitoring
end
end
 
// ✅ FIX 2: If you want to stop the test, use disable or $finish
initial begin
forever begin
@(posedge clk);
if (error_flag) begin $fatal(1, "Fatal error"); end  // ends sim
end
end

// ❌ BUG: continue re-enters forever body immediately (no time advance)
initial begin
forever begin
if (!valid) continue;  // ❌ skips to next forever iteration
// but there's no timing before this check!
// valid never changes → zero-time loop
$display("%h", data);
end
end
// Simulation: hangs at time 0. CPU=100%. No output. Same as forgetting @.
 
// ✅ FIX: ALWAYS have a timing control before continue in forever
initial begin
forever begin
@(posedge clk);         // ✅ timing BEFORE the continue check
if (!valid) continue;  // ✅ safe: re-enters AFTER next posedge
$display("%h", data);
end
end

// ❌ BUG: task returns early but leaves valid=1 asserted permanently
task automatic drive_packet(input int size, input logic [7:0] payload[]);
if (size <= 0) return;   // ❌ returns but valid/ready may be asserted!
 
valid = 1'b1;
for (int i = 0; i < size; i++) begin
data = payload[i];
@(posedge clk);
if (bus_error) return;   // ❌ returns mid-burst, valid still=1!
// DUT sees endless burst after task exits
end
valid = 1'b0;  // this is only reached if loop completes normally
endtask
 
// ✅ FIX: always clean up signals before return (or use defer-style cleanup)
task automatic drive_packet(input int size, input logic [7:0] payload[]);
if (size <= 0) return;   // safe — valid not yet asserted
 
valid = 1'b1;
for (int i = 0; i < size; i++) begin
data = payload[i];
@(posedge clk);
if (bus_error) begin
valid = 1'b0;     // ✅ clean up BEFORE return
$error("Bus error at beat %0d", i);
return;
end
end
valid = 1'b0;
endtask

// ❌ BUG: label name typo — 'seach_blk' instead of 'search_blk'
initial begin
begin : search_blk                  // ← correct label here
for (int i = 0; i < 16; i++) begin
if (mem[i] == target) begin
found_idx = i;
disable seach_blk;   // ❌ TYPO: 'seach' not 'search'
// In some simulators: compile error
// In others: runtime — no effect!
// Loop runs all 16 iterations
// found_idx = last match (not first)
end
end
found_idx = -1;               // this runs even after match!
end
end
 
// ✅ FIX: use break for simple in-loop exit (no label needed)
initial begin
found_idx = -1;
for (int i = 0; i < 16; i++) begin
if (mem[i] == target) begin
found_idx = i;
break;   // ✅ no label required, no typo risk
end
end
end

// ❌ BUG: disable fork kills the coverage sampler along with the stimulus
initial begin
fork
stimulus_driver();     // drives 1000 transactions
coverage_sampler();    // needs to run AFTER stimulus finishes
watchdog();
join_any
disable fork;             // ❌ kills ALL — coverage sampler killed too!
// Coverage never completes — coverage reports are incomplete
end
 
// ✅ FIX: use named labels to kill only specific threads
initial begin
fork
begin : stim_proc   stimulus_driver();  end
begin : cov_proc    coverage_sampler(); end
begin : wdog_proc   watchdog();         end
join_any
disable stim_proc;    // ✅ kill only stimulus
disable wdog_proc;    // ✅ kill only watchdog
// coverage sampler (cov_proc) continues running
end

// ❌ BUG: engineer expected break to exit both loops — it only exits inner
initial begin
for (int r = 0; r < 8; r++) begin    // outer: row 0..7
for (int c = 0; c < 8; c++) begin  // inner: col 0..7
if (mem[r][c] == target) begin
found_r = r; found_c = c;
break;     // ❌ exits INNER loop only!
// Outer loop continues from r=found_r+1
// More searches happen → found_r/found_c overwritten
end
end
end
end
 
// ✅ FIX: use a 'found' flag to gate the outer loop
initial begin
bit found = 0;
found_r = -1; found_c = -1;
for (int r = 0; r < 8 && !found; r++) begin
for (int c = 0; c < 8; c++) begin
if (mem[r][c] == target) begin
found_r = r; found_c = c;
found = 1;
break;         // ✅ exits inner, outer checks !found
end
end
end
end

// ❌ BUG: function has no return on the else path
function automatic logic [7:0] compute(input logic [7:0] a, b);
if (a > b) begin
return a - b;   // path A: explicit return ✅
end
// path B: no return statement!
// SystemVerilog: function implicitly returns function_name variable
// which was never assigned → returns 0 (or X in 4-state)
// Simulation: returns 0 when a <= b
// This matches "b - a = 0 when a==b" accidentally → test passes
// But when a=3, b=5: returns 0 instead of 5-3=2 — WRONG!
endfunction
 
// ✅ FIX: always have an explicit return on every path
function automatic logic [7:0] compute(input logic [7:0] a, b);
if (a > b) return a - b;   // ✅ path A
return b - a;                  // ✅ path B — abs(a-b)
endfunction
// Lint tools catch "function may have no return on all paths" — treat as ERROR

// ❌ BUG: continue skips remaining body but keeps looping
// Engineer wanted to stop at first match — used continue instead of break
always_comb begin
first_set = 4'hF;
for (int i = 0; i < 8; i++) begin
if (!data[i]) continue;  // skip iterations where data[i]=0
first_set = i[3:0];        // ← BUT this runs for EVERY set bit!
// Result: first_set = LAST set bit (not first)
// RTL synthesis: not a priority encoder — last-wins mux chain
end
end
 
// Example: data=8'b0001_0100 (bits 2 and 4 set)
// With continue: first_set = 4 (last set bit) ❌
// With break:    first_set = 2 (first set bit) ✅
 
// ✅ FIX: use break to stop at first match
always_comb begin
first_set = 4'hF;
for (int i = 0; i < 8; i++) begin
if (data[i]) begin
first_set = i[3:0];
break;   // ✅ stops at first match — priority encoder behavior
end
end
end