Reduction Operators

logic [7:0] data = 8'hA5;   // 1010_0101  — 4 ones (even count)
bit          result;
 
// ── Six reduction operators ─────────────────────────────────────
result = &data;    // AND:  0 — not all bits are 1
result = ~&data;   // NAND: 1 — at least one bit is 0
result = |data;    // OR:   1 — at least one bit is 1
result = ~|data;   // NOR:  0 — value is not zero
result = ^data;    // XOR:  0 — even number of 1s (4 ones)
result = ~^data;   // XNOR: 1 — even parity (complement of XOR)
 
// ── Reduction on concatenation ──────────────────────────────────
logic [3:0] a = 4'hF, b = 4'h0;
result = &{a, b};   // AND all 8 bits: 1111_0000 → 0 (not all 1)
result =  ^{a, b};   // XOR all 8 bits: parity of combined vector
 
// ── Common inline patterns ──────────────────────────────────────
if (|req_bus)        handle_requests();   // any request pending?
if (&grant_bus)      $display("all granted"); // all grants asserted?
if (~|error_flags)   mark_pass();         // no errors?
parity_bit = ^payload;                      // generate odd parity

logic [31:0] word = 32'hA5A5_A5A5;
 
// Reduce only a specific slice
bit upper_parity = ^word[31:16];   // parity of upper 16 bits
bit lower_any    = |word[7:0];    // any bit set in lowest byte?
bit nibble_all   = &word[3:0];    // all bits set in lowest nibble?
 
// Build even-parity byte: data + parity such that ^{data, parity} = 0
logic [7:0] payload  = 8'hA5;
logic        parity   = ^payload;    // 0 (even count of 1s in A5)
logic [8:0] protected = {parity, payload};
// Receiver checks: ^protected should = 0 for no error
$display("Parity check: %0b (0=ok)", ^protected);   // 0

module tb_reduction_basic;
 
logic [7:0] v_all1 = 8'hFF;   // 1111_1111
logic [7:0] v_all0 = 8'h00;   // 0000_0000
logic [7:0] v_mix  = 8'hA5;   // 1010_0101 (even parity)
logic [7:0] v_odd  = 8'hA7;   // 1010_0111 (odd parity)
 
initial begin
$display("=== ALL-ONES vector (0xFF) ===");
$display(" &v = %b  (all 1?)", &v_all1);    // 1
$display(" |v = %b  (any 1?)", |v_all1);    // 1
$display(" ^v = %b  (odd par?)", ^v_all1);   // 0 (8 ones = even)
 
$display("=== ALL-ZEROS vector (0x00) ===");
$display(" &v = %b  (all 1?)", &v_all0);    // 0
$display(" |v = %b  (any 1?)", |v_all0);    // 0
$display("~|v = %b  (zero?)",  ~|v_all0);   // 1
 
$display("=== MIXED vector (0xA5) — 4 ones, even parity ===");
$display(" &v = %b", &v_mix);    // 0
$display(" |v = %b", |v_mix);    // 1
$display(" ^v = %b  (0=even)", ^v_mix);   // 0
$display("~^v = %b  (1=even)", ~^v_mix);  // 1
 
$display("=== ODD parity vector (0xA7) — 5 ones ===");
$display(" ^v = %b  (1=odd)",  ^v_odd);    // 1
$display("~^v = %b  (0=odd)",  ~^v_odd);   // 0
 
$finish;
end
 
endmodule

module tb_parity;
 
logic [7:0] payload;
logic        tx_parity;
logic [8:0] tx_word;    // {parity, data} — 9 bits
 
logic [8:0] rx_word;
logic        rx_parity_check;
 
task automatic test_parity(input logic [7:0] data, input bit inject_err);
payload   = data;
tx_parity = ^payload;              // odd parity bit — make total 1-count odd
tx_word   = {tx_parity, payload};
 
$display("TX: data=%08b  parity=%b  word=%09b",
payload, tx_parity, tx_word);
 
rx_word = tx_word;
if (inject_err) rx_word[3] = ~rx_word[3];   // flip bit 3
 
// Receiver: ^rx_word should be 1 for odd parity (no error)
rx_parity_check = ^rx_word;
 
if (rx_parity_check)
$display("RX: OK   — parity check passed\n");
else
$error("RX: ERROR — parity failure (even count = error)\n");
endtask
 
initial begin
test_parity(8'hA5, 0);   // clean transmission
test_parity(8'hA5, 1);   // one bit flipped — parity detects it
$finish;
end
 
endmodule

TX: data=10100101  parity=0  word=010100101
RX: OK   — parity check passed
 
TX: data=10100101  parity=0  word=010100101
ERROR: RX: ERROR — parity failure (even count = error)

// ── 1. Any pending interrupt — OR reduction ────────────────────────
logic [7:0] irq_flags;
if (|irq_flags)
handle_interrupt();    // any bit set → at least one IRQ pending
 
// ── 2. All arbitration grants asserted — AND reduction ─────────────
logic [3:0] grant;
assert property (@(posedge clk)
all_grant_en |-> ##1 (&grant))
else $error("Not all grants asserted");
 
// ── 3. Zero check — NOR reduction ─────────────────────────────────
logic [15:0] addr_bus;
if (~|addr_bus)
$warning("Address bus is zero — is this intentional?");
 
// ── 4. One-hot validation — manual check using reduction ──────────
function bit is_onehot(input logic [7:0] v);
// Exactly one bit set: v != 0 AND (v & (v-1)) == 0
// (v-1) clears the lowest set bit and sets all lower bits)
return (|v) && (~|(v & (v - 8'h1)));
endfunction
 
// Or use the built-in system function:
if ($onehot(sel_bus))
$display("One-hot valid");
 
// ── 5. Parity check in scoreboard ────────────────────────────────
function void check_parity(
input logic [7:0] data,
input logic        received_parity
);
logic expected_parity = ^data;
if (expected_parity !== received_parity)
$error("Parity mismatch: data=%08b exp_par=%b rcv_par=%b",
data, expected_parity, received_parity);
endfunction

module tb_reduction_x;
 
logic [7:0] sig_x = 8'bxxxx_xxxx;   // all X — uninitialized
logic [7:0] sig_p = 8'b1010_x101;   // partial X — one bit unknown
 
initial begin
// AND: 0 absorbs — if any bit is 0, result is 0
// But all X: no 0 to absorb, result is X
$display("&all_X     = %b", &sig_x);    // x
$display("|all_X     = %b", |sig_x);    // x
$display("^all_X     = %b", ^sig_x);    // x
 
// Partial X: AND checks for 0 absorbing
$display("&partial_X = %b", &sig_p);   // x (no 0 bit to absorb)
 
// If any bit is 0, AND absorbs regardless of X
logic [7:0] sig_has0 = 8'b0xxx_xxxx; // has a 0 at bit 7
$display("&has_0     = %b", &sig_has0);  // 0 — absorbed!
 
// XOR: NO absorption — any X propagates
$display("^partial_X = %b", ^sig_p);    // x — one X contaminates
 
$finish;
end
 
endmodule

&all_X     = x
|all_X     = x
^all_X     = x
&partial_X = x
&has_0     = 0
^partial_X = x

// ── 1. IRQ monitor — detect any active interrupt ──────────────────
always @(posedge clk) begin
if (|irq_vec && irq_en)
$display("[MON] IRQ active: vec=0x%0h", irq_vec);
end
 
// ── 2. Bus protocol monitor — check all valid signals asserted ────
assert property (
@(posedge clk) start_burst |-> ##1 (&{awvalid, wvalid, bready})
) else $error("AXI write burst: not all handshake signals asserted");
 
// ── 3. Coverage model — parity coverage ──────────────────────────
covergroup cg_parity;
cp_parity: coverpoint (^payload) {
bins even_parity = {0};
bins odd_parity  = {1};
}
endgroup
 
// ── 4. One-hot checker in arbitration verification ────────────────
always @(posedge clk) begin
if (|grant_bus && !$onehot(grant_bus))
$error("[ARB] Multiple grants asserted: 0x%0h", grant_bus);
end
 
// ── 5. Post-reset X check — ensure no X after reset deassert ─────
task automatic check_no_x_post_reset(input logic [31:0] sig, input string name);
if ($isunknown(sig))
$error("[RESET] %s has X after reset: %b", name, sig);
else if (|sig)   // safe to use | now that X is ruled out
$warning("[RESET] %s is nonzero after reset: 0x%0h", name, sig);
endtask

logic [7:0] dut_data;    // DUT output — may have X if undriven
logic        dut_parity;  // DUT parity output
 
// BUGGY: if dut_data has ANY X bit, ^dut_data = X
// The !== comparison then returns 1 (X !== clean bit) — looks like parity error
// But the real root cause is an X on the data bus, not a parity computation failure
if (^dut_data !== dut_parity)
$error("Parity error");   // fires on X — but misleading error message

// CORRECT: screen for X first — separate root causes
if ($isunknown(dut_data)) begin
$error("X on data bus — cannot check parity: %b", dut_data);
end else if (^dut_data !== dut_parity) begin
$error("Parity MISMATCH: data=%08b exp_par=%b got_par=%b",
dut_data, ^dut_data, dut_parity);
end

logic [7:0] status = 8'hxx;   // uninitialized — all X
 
// BUGGY: |status = X when status is all-X
// X in if = false → branch skipped → no IRQ handled — false pass
if (|status)
handle_irq();   // never fires when status is X — wrong behavior
 
// CORRECT: use !== 0 to detect X as nonzero, or screen X first
if ($isunknown(status))
$error("Status register has X — check DUT reset");
else if (|status)
handle_irq();

logic [7:0] grant = 8'hFF;   // all 8 channels granted
 
// BUGGY: typo — checking only bits [3:0], not [7:0]
if (&grant[3:0])
$display("All grants active");   // fires even if grants[7:4] are 0
 
// CORRECT: reduce the full vector
if (&grant)
$display("All 8 grants active");