Type Casting & Conversion

// ── 1. STATIC CAST: type'(expression) ────────────────────────────
 
// Width cast — narrows or widens
logic [31:0] wide = 32'hAABBCCDD;
logic [7:0]  narrow = 8'(wide);      // keep lower 8 bits: DD
logic [15:0] mid    = 16'(wide);     // keep lower 16 bits: CCDD
 
// Integer type cast
real   r = 3.9;
int    i = int'(r);             // truncates: i = 3 (NOT 4)
real   back = real'(i);         // promotes: back = 3.0
 
// Signedness cast — same bits, different interpretation
logic [7:0] raw = 8'hFF;
int          as_s = int signed'(raw);    // -1 (sign-extended)
int          as_u = int unsigned'(raw);  // 255
 
// Enum cast (bypasses validation — use $cast for safety)
typedef enum logic [1:0] { A, B, C } abc_t;
abc_t val = abc_t'(2'b01);              // = B — no validity check
 
// Packed struct ↔ logic
typedef struct packed { logic[7:0] hi; logic[7:0] lo; } word_t;
word_t   w  = word_t'(16'hABCD);  // {hi:AB, lo:CD}
logic [15:0] lv = 16'(w);             // ABCD
 
// ── 2. $signed() / $unsigned() ────────────────────────────────────
// Reinterpret sign context WITHOUT changing bits
 
logic [7:0] u = 8'hFF;   // unsigned: 255
$display("%0d", u);               // 255 (unsigned context)
$display("%0d", $signed(u));   // -1  (same bits, signed context)
 
logic signed [7:0] s = -1;   // signed: -1 = 8'hFF
$display("%0d", s);               // -1
$display("%0d", $unsigned(s));  // 255
 
// Arithmetic right shift on unsigned type — needs $signed
logic [7:0] raw2 = 8'hF8;          // -8 if treated as signed
$display("%0d", raw2 >>> 2);       // 62 — unsigned: zero-fill
$display("%0d", $signed(raw2) >>> 2); // -2 — sign-fill
 
// ── 3. $cast(dest, src) — dynamic, validated ─────────────────────
 
// Enum validation
abc_t e;
int   n = 5;
if ($cast(e, n))
$display("cast OK: %s", e.name());
else
$display("cast FAIL: %0d not a valid abc_t", n);   // prints this
 
// Class hierarchy downcast
// class Base; endclass
// class Derived extends Base; endclass
// Base b = new Derived();   // upcast is implicit and safe
// Derived d;
// if (!$cast(d, b)) $error("not a Derived instance");
 
// ── 4. $bits() — query bit width ─────────────────────────────────
$display("$bits(logic [7:0]) = %0d", $bits(logic[7:0]));  // 8
$display("$bits(int)         = %0d", $bits(int));          // 32
$display("$bits(word_t)      = %0d", $bits(word_t));       // 16

module tb_cast_basics;
 
initial begin
 
// ── Width narrowing (explicit) ────────────────────────────────
logic [31:0] wide = 32'hAABBCCDD;
logic [7:0]  low8 = 8'(wide);       // explicit: keep lower 8
$display("8'(AABBCCDD) = 0x%02h", low8);   // DD
 
// ── Width widening ────────────────────────────────────────────
logic [7:0]  narrow_u = 8'hFF;
logic [15:0] wide_u   = 16'(narrow_u);   // 16'h00FF (zero-extend)
$display("zero-ext 8'hFF: 0x%04h", wide_u);  // 00FF
 
logic signed [7:0]  narrow_s = -1;      // 8'hFF
logic signed [15:0] wide_s   = 16'(narrow_s); // 16'hFFFF (sign-extend)
$display("sign-ext -1:   0x%04h", wide_s);   // FFFF
 
// ── $signed: reinterpret as signed without changing bits ──────
logic [7:0] u = 8'hFF;
$display("unsigned: %0d", u);             // 255
$display("signed:   %0d", $signed(u));   // -1
 
// ── 4-state → 2-state: X silently becomes 0 ──────────────────
logic [7:0] x_val = 8'hXX;
bit   [7:0] b_val  = x_val;              // X → 0 silently!
$display("logic X → bit: 0x%02h", b_val); // 00
 
// ── real ↔ int ────────────────────────────────────────────────
real r = 3.9;
int  n = int'(r);
$display("int'(3.9)  = %0d", n);   // 3 (truncates)
n = int'($round(r));
$display("round(3.9) = %0d", n);   // 4 (rounded)
 
$finish;
end
 
endmodule

module tb_sign_context;
 
initial begin
 
// ── Mixed signed/unsigned comparison trap ─────────────────────
int          s  = -1;   // signed: -1
int unsigned u  = 1;    // unsigned: 1
 
// Comparing signed and unsigned: signed promoted to unsigned!
// -1 as unsigned = 0xFFFFFFFF = 4294967295
if (s > u)
$display("-1 > 1 = TRUE  (signed promoted to unsigned!)");
 
// FIX: cast both to same sign type
if ($signed(s) > $signed(u))
$display("-1 > 1 signed = TRUE  (still -1 > 1 when both signed)");
else
$display("-1 < 1 signed = correct");   // prints
 
// ── $signed for arithmetic right shift on unsigned type ───────
logic [7:0] raw = 8'hF8;   // 1111_1000 = -8 if signed
 
$display("raw >>> 2 (unsigned): %0d", raw >>> 2);            // 62
$display("raw >>> 2 (signed):   %0d", $signed(raw) >>> 2);  // -2
 
// ── Signed extension when widening ────────────────────────────
logic signed [7:0]  s8  = -10;     // 8'hF6
logic signed [15:0] s16;
 
s16 = s8;           // implicit: sign-extends → 16'hFFF6 = -10
$display("s8=-10 → s16=%0d (0x%04h)", s16, s16);  // -10, FFF6
 
s16 = 16'(s8);      // explicit static cast: same sign-extend result
$display("16'(s8) = %0d", s16);  // -10
 
$finish;
end
 
endmodule

// ── Enum $cast ────────────────────────────────────────────────────
typedef enum logic [1:0] { IDLE, RUN, DONE } state_t;
 
function automatic bit safe_set_state(ref state_t s, input int raw);
if (!$cast(s, raw)) begin
$error("Invalid state value %0d — ignoring", raw);
return 0;
end
$display("State set to: %s", s.name());
return 1;
endfunction
 
// ── Class hierarchy $cast ─────────────────────────────────────────
class base_txn;
int id;
function new(int i); id = i; endfunction
endclass
 
class axi_txn extends base_txn;
logic [31:0] addr;
function new(int i, logic[31:0] a); super.new(i); addr=a; endfunction
endclass
 
module tb_cast_demo;
initial begin
state_t s;
 
safe_set_state(s, 1);   // OK: RUN
safe_set_state(s, 3);   // ERROR: 3 not in IDLE/RUN/DONE
 
// Upcast (implicit, always safe)
base_txn base_h = new axi_txn(1, 32'hA000);  // OK: axi_txn IS-A base_txn
 
// Downcast (needs $cast — may fail at runtime)
axi_txn axi_h;
if ($cast(axi_h, base_h)) begin
$display("Downcast OK: addr=0x%08h", axi_h.addr);  // A000_0000
end else
$error("Not an axi_txn");
 
// Downcast to wrong type — $cast returns 0, no crash
base_txn plain_h = new base_txn(99);
if (!$cast(axi_h, plain_h))
$display("Downcast FAIL: plain_h is not an axi_txn");  // prints
 
$finish;
end
endmodule

module tb_cast_patterns;
 
typedef struct packed {
logic [7:0] hi;
logic [7:0] lo;
} word16_t;
 
initial begin
 
// ── Integer division → real (cast before dividing!) ───────────
int covered = 75, total = 100;
$display("WRONG: %0.1f%%", covered / total * 100.0);       // 0.0%
$display("RIGHT: %0.1f%%", real'(covered) / real'(total) * 100.0); // 75.0%
 
// ── Packed struct ↔ logic vector ──────────────────────────────
word16_t w;
logic [15:0] raw = 16'hABCD;
 
w = word16_t'(raw);    // raw → struct: hi=AB, lo=CD
$display("hi=%02h lo=%02h", w.hi, w.lo);
 
raw = 16'(w);          // struct → raw: ABCD
$display("raw = 0x%04h", raw);
 
// ── $bits() for dynamic width query ──────────────────────────
$display("$bits(word16_t) = %0d", $bits(word16_t));  // 16
$display("$bits(int)      = %0d", $bits(int));       // 32
$display("$bits(real)     = %0d", $bits(real));      // 64
 
// ── Longint cast to avoid sum overflow ────────────────────────
int counts [4] = '{1500000000, 1500000000, 1, 1};
int     bad_sum  = counts.sum();                          // OVERFLOW
longint good_sum = counts.sum() with (longint'(item));   // safe
$display("bad_sum  = %0d", bad_sum);   // wrong (negative)
$display("good_sum = %0d", good_sum);  // 3000000002
 
$finish;
end
 
endmodule

// ── 1. COVERAGE PERCENTAGE: cast before divide ────────────────────
function automatic real coverage_pct(int covered, total);
return (real'(covered) / real'(total)) * 100.0;
endfunction
 
// ── 2. PACKET FIELD EXTRACTION: struct cast from raw ──────────────
ctrl_reg_t ctrl = ctrl_reg_t'(bus_readback);
$display("timeout=%0d", ctrl.timeout);
 
// ── 3. SIGNED COMPARISON IN SCOREBOARD ───────────────────────────
logic [31:0] dut_result;
int           exp_signed = -10;
// Compare treating DUT output as signed
if ($signed(dut_result) !== exp_signed)
$error("Signed mismatch: exp=%0d got=%0d",
exp_signed, $signed(dut_result));
 
// ── 4. UVM DOWNCAST (pattern used everywhere in UVM) ──────────────
// In a UVM scoreboard write() task:
// task write(uvm_sequence_item item);
//   axi_seq_item txn;
//   if (!$cast(txn, item))
//     `uvm_fatal("CAST", "Expected axi_seq_item")
//   check_txn(txn);
// endtask
 
// ── 5. LATENCY MEASUREMENT: int → longint for large values ────────
longint t_req = $time;
// ... wait ...
int latency = int'($time - t_req);  // safe if latency < 2B cycles
 
// ── 6. STROBE-MASKED BYTE COMPARE ─────────────────────────────────
function automatic bit bytes_match_with_strobe(
logic [31:0] exp, got, logic [3:0] strb
);
for (int i=0; i<4; i++) begin
if (strb[i]) begin
logic[7:0] e = 8'(exp >> (i*8));  // extract byte via cast
logic[7:0] g = 8'(got >> (i*8));
if (e !== g) return 0;
end
end
return 1;
endfunction

int covered = 75, total = 100;
 
// BUGGY: integer division happens first → 75/100 = 0 → 0 * 100.0 = 0.0
real pct = covered / total * 100.0;
$display("Coverage: %0.1f%%", pct);   // 0.0% — wrong!
 
// FIXED: cast at least one operand BEFORE the division
pct = real'(covered) / real'(total) * 100.0;
$display("Coverage: %0.1f%%", pct);   // 75.0% — correct

int    wide_result = 32'hAABBCCDD;
byte   narrow;
 
// BUGGY IMPLICIT: upper 24 bits silently dropped — no warning
narrow = wide_result;   // keeps only lower 8: DD
$display("implicit: 0x%02h", narrow);  // DD — looks valid, upper bits gone
 
// EXPLICIT: same result but intent is clear
narrow = byte'(wide_result);  // explicit truncation
$display("explicit: 0x%02h", narrow);  // DD
 
// CORRECT if you need to detect overflow:
if (wide_result > 127 || wide_result < -128)
$error("Value doesn't fit in byte: %0d", wide_result);

logic [7:0] data = 8'hF8;   // = -8 when interpreted as signed
 
// BUGGY: $signed() applied AFTER shift — shift was already unsigned
logic signed [7:0] wrong = $signed(data >>> 2);
$display("wrong: %0d", wrong);   // 62 — unsigned shift first, then reinterp
 
// CORRECT: $signed() before the shift — shift executes in signed context
logic signed [7:0] right = $signed(data) >>> 2;
$display("right: %0d", right);   // -2 — arithmetic right shift

typedef enum logic [1:0] { IDLE, RUN, DONE } state_t;
state_t s;
int     raw = 3;   // 3 is NOT a valid state (only 0,1,2 defined)
 
// BUGGY: static cast — no validation, illegal value silently stored
s = state_t'(raw);       // compiles; s.name() returns "" — illegal state
$display("name: '%s'", s.name());  // "" — red flag!
 
// CORRECT: $cast — validates and reports failure
if (!$cast(s, raw))
$error("Cannot set state to %0d — not a valid state_t value", raw);
// $error fires — no illegal state reaches the FSM