4-State vs 2-State Types

// ── 4-STATE TYPES ────────────────────────────────────────────────
logic              single_bit;     // 1-bit 4-state — default X at start
logic [7:0]         byte_sig;       // 8-bit 4-state vector
logic [31:0]        word_sig;       // 32-bit 4-state
logic signed [7:0] s_byte;         // signed 4-state byte
 
// wire — driven by assign or port; cannot be driven by always/initial alone
wire               net_a;          // single bit net — default value Z (undriven)
wire [7:0]          bus_a;          // 8-bit net
 
// reg — legacy: same as logic for simulation, avoid in new code
reg  [7:0]          old_style;      // avoid in SV — use logic
 
// ── 2-STATE TYPES ────────────────────────────────────────────────
bit                flag;           // 1-bit 2-state — initializes to 0
bit  [7:0]          byte_2s;        // 8-bit 2-state vector
bit  [31:0]         word_2s;        // 32-bit — initializes to 0
bit  signed [7:0] sb;              // signed 2-state byte
 
// ── KEY BEHAVIORAL DIFFERENCE ────────────────────────────────────
logic [7:0] l;  // l = 8'hxx  at time 0 (X)
bit   [7:0] b;  // b = 8'h00  at time 0 (0)
 
// ── logic in RTL: driven from assign OR always block (SV advantage)
logic [7:0] out;
assign out = in_a & in_b;         // OK: continuous assign
 
logic [7:0] reg_out;
always_ff @(posedge clk)          // OK: procedural assign — this was only valid
reg_out <= data_in;              // for 'reg' in Verilog, now 'logic' works too
 
// ── wire restriction: cannot be driven from initial/always alone
wire [7:0] w;
// always_comb w = x;  ← ILLEGAL for wire — use logic instead
assign w = some_signal;           // OK: continuous assignment

module tb_init_comparison;
 
logic [7:0] l_val;      // 4-state: starts as X
bit   [7:0] b_val;      // 2-state: starts as 0
wire  [7:0] w_val;      // net: starts as Z (undriven)
 
initial begin
// At time 0, before anything is driven:
$display("logic at t=0: %h",  l_val);   // xx
$display("bit   at t=0: %h",  b_val);   // 00
$display("wire  at t=0: %h",  w_val);   // zz
 
// Use === (case equality) to detect X and Z reliably
$display("l_val is X: %0b",  l_val === 8'hxx);  // 1 — correctly detected
$display("b_val is X: %0b",  b_val === 8'hxx);  // 0 — no X possible
$display("w_val is Z: %0b",  w_val === 8'hzz);  // 1 — undriven net
 
// X in if condition — the silent false behavior
if (l_val)
$display("logic: if-branch");
else
$display("logic: else-branch");
// Neither prints when l_val is X!
$display("(nothing printed above — X condition skips both branches)");
 
// Assign X-valued logic to bit: silent conversion
b_val = l_val;
$display("b_val after = l_val (was X): %h", b_val);  // 00 — X became 0!
 
$finish;
end
 
endmodule

logic at t=0: xx
bit   at t=0: 00
wire  at t=0: zz
l_val is X: 1
b_val is X: 0
w_val is Z: 1
(nothing printed above — X condition skips both branches)
b_val after = l_val (was X): 00

module tb_x_propagation;
 
logic [7:0] a, b, result;
 
initial begin
// Propagation through AND
a = 8'hXX; b = 8'hFF;
result = a & b;
$display("XX & FF = %h", result);    // xx — X propagates
 
a = 8'hXX; b = 8'h00;
result = a & b;
$display("XX & 00 = %h", result);    // 00 — AND with 0 dominates
 
// Propagation through OR
a = 8'hXX; b = 8'h00;
result = a | b;
$display("XX | 00 = %h", result);    // xx — OR with 0 propagates X
 
a = 8'hXX; b = 8'hFF;
result = a | b;
$display("XX | FF = %h", result);    // ff — OR with 1 dominates
 
// Partial X — some bits unknown, others masked
a = 8'b1111_XXXX; b = 8'hF0;
result = a & b;
$display("1111XXXX & F0 = %b", result); // 1111_0000 — lower X bits ANDed with 0
 
a = 8'b1111_XXXX; b = 8'hFF;
result = a & b;
$display("1111XXXX & FF = %b", result); // 1111_xxxx — X bits survive
 
// === vs == for X detection
a = 8'hXX;
$display("a == 8'hXX : %0b", a == 8'hXX);  // X — logical == propagates X
$display("a === 8'hXX: %0b", a === 8'hXX); // 1 — case equality detects X
 
$finish;
end
 
endmodule

module tb_scoreboard_types;
 
logic [7:0] dut_output;    // DUT output — starts as X (no reset yet)
bit   [7:0] ref_model_bad; // WRONG: bit reference — initializes to 0
logic [7:0] ref_model_ok;  // CORRECT: logic reference — initializes to X
 
initial begin
// Simulate pre-reset: DUT hasn't been reset, output is X
// dut_output is never assigned — stays X
 
// DANGEROUS CHECK: bit reference masks the bug
if (dut_output !== ref_model_bad)
$error("BAD_SB MISMATCH");      // fires? Let's check...
// dut_output = XX, ref_model_bad = 00
// XX !== 00 → TRUE → $error fires... but only because !== sees X
// Now what if someone uses == instead of !==?
 
if (dut_output == ref_model_bad)
$display("BAD_SB: looks like PASS");  // evaluates to X → treated as false
// Neither branch executes! Silent pass of a real bug.
 
// CORRECT CHECK: logic reference, use !== for case inequality
if (dut_output !== ref_model_ok)
$error("GOOD_SB MISMATCH: DUT output is X — no reset?");
// Both are X → XX !== XX → FALSE → no error
// But we should still check for X explicitly!
if (^dut_output === 1'bX)
$error("DUT output contains X — check reset sequence");
 
$finish;
end
 
endmodule

module tb_multi_driver;
 
wire  shared_wire;        // wire: supports multiple drivers with resolution
logic shared_logic = 0;  // logic: only ONE continuous driver allowed
 
// wire: two drivers — resolved using wired-AND/wired-OR table
assign shared_wire = 1'b0;    // driver 1
assign shared_wire = 1'b1;    // driver 2 — conflict → X
// shared_wire = X (both strong drivers conflict)
 
// Tri-state bus modeled correctly with wire
logic oe1, oe2, drv1, drv2;
wire  data_bus;
assign data_bus = oe1 ? drv1 : 1'bz;  // driver 1: active when oe1=1
assign data_bus = oe2 ? drv2 : 1'bz;  // driver 2: active when oe2=1
// When only one oe is active, the bus is cleanly driven
// When both oe are active with different values → X
// When neither oe is active → Z (high impedance)
 
initial begin
oe1 = 1; drv1 = 1; oe2 = 0; drv2 = 0;
#1;
$display("Bus (oe1 only): %b", data_bus);  // 1
 
oe1 = 0; oe2 = 0;
#1;
$display("Bus (no driver): %b", data_bus); // z
 
oe1 = 1; drv1 = 0; oe2 = 1; drv2 = 1;
#1;
$display("Bus (conflict): %b", data_bus);  // x
 
$finish;
end
 
endmodule

// ── 1. INTERFACE SIGNALS: always logic ────────────────────────────
interface axi_if (input logic clk);
logic        awvalid, awready;
logic [31:0] awaddr;           // logic: X at start reveals undriven signals
logic [7:0]  awlen;
endinterface
 
// ── 2. SCOREBOARD: logic for comparisons, bit for counters ─────────
class axi_scoreboard;
logic [31:0] exp_data;     // logic: X means "not yet computed"
logic [31:0] got_data;     // logic: X means "not yet captured"
int           pass_count;   // int: pure counter, X never meaningful
int           fail_count;
 
task check(logic [31:0] exp, got);
// Step 1: detect X in DUT output — always a bug
if (^got === 1'bX)
$error("DUT output contains X");
// Step 2: use !== for comparison (detects X differences)
else if (exp !== got)
fail_count++;
else
pass_count++;
endtask
endclass
 
// ── 3. SVA ASSERTIONS: logic for RTL signals ──────────────────────
// assert property (@(posedge clk) awvalid |-> ##[1:3] awready);
// awvalid is logic — X on awvalid won't trigger the assertion
// Use $isunknown() for explicit X detection in SVA
 
// ── 4. DRIVER: drive using logic values including Z ────────────────
task automatic drive_bus(ref logic [7:0] bus, input bit oe, input logic [7:0] val);
bus = oe ? val : 8'hzz;    // drive Z when output-enable is low
endtask
 
// ── 5. CONSTRAINTS: bit is fine for rand variables ────────────────
class rand_txn;
rand bit  [7:0] len;    // bit is fine — constraint solver never generates X/Z
rand bit  [1:0] btype;
rand logic [31:0] addr;  // logic fine for rand too — solver won't produce X
endclass

// BUGGY: reference model uses bit — starts at 0
bit [31:0] ref_data;      // = 0 at start
logic [31:0] dut_data;    // = X at start (DUT not yet reset)
 
if (dut_data == ref_data)  // X == 0 → evaluates to X → neither branch!
$display("PASS");         // doesn't print
else
$error("FAIL");           // doesn't print either — bug silently passes!
 
// Waveform clue: scoreboard shows no pass/fail events at all during reset
// Engineer assumes "the checker hasn't started yet" — it started, it just found X
 
// FIXED: use logic for reference model, !== for comparison
logic [31:0] ref_data_ok;  // = X at start — matches DUT state honestly
if (^dut_data === 1'bX)     // explicitly detect X first
$error("DUT output is X — no reset applied yet");
else if (dut_data !== ref_data_ok)
$error("MISMATCH");

module bad_rtl (input logic clk, input logic d, output wire q);
// BUGGY: wire cannot be driven from always_ff in Verilog
always_ff @(posedge clk)
q <= d;   // ERROR: cannot drive wire from procedural block
endmodule
 
// FIXED: use logic (or reg in Verilog)
module good_rtl (input logic clk, input logic d, output logic q);
always_ff @(posedge clk)
q <= d;   // OK: logic works with both continuous and procedural
endmodule
 
// Note: many tools silently accept wire in procedural blocks and infer
// a latch. This is a portability bug — always use logic for procedural.

logic [7:0] dut_out;         // X before reset
logic [7:0] expected = 8'h00;
 
// BUGGY: == propagates X — if condition is X, checker silently skips
if (dut_out == expected)
pass_count++;      // never executes when dut_out is X
else
fail_count++;      // never executes either — both branches skipped!
// Symptom: pass_count and fail_count both stay at 0 during reset
 
// CORRECT: !== catches X mismatches; the else branch always fires for X
if (dut_out !== expected)
fail_count++;      // fires for ANY non-match including X != 00
else
pass_count++;      // only fires for exact binary match
 
// BEST PRACTICE: check for X explicitly first
if (^dut_out === 1'bX)
$error("X in DUT output — check reset");
else if (dut_out !== expected)
$error("Mismatch: exp=%h got=%h", expected, dut_out);

logic [1:0] state;     // X at start — FSM not yet reset
 
// BUGGY: casex treats X in the expression as wildcard
// state = X means X matches EVERY case item → first match executes!
casex (state)           // dangerous with X in state
2'b00: $display("IDLE");   // may execute even if state is X!
2'b01: $display("RUN");
2'b10: $display("DONE");
default: $display("UNKNOWN");
endcase
 
// CORRECT: use case (not casex) and add explicit X check
if (^state === 1'bX)
$display("FSM state is X — reset not applied");
else
case (state)            // plain case: X in state matches nothing except default
2'b00: $display("IDLE");
2'b01: $display("RUN");
2'b10: $display("DONE");
default: $display("UNKNOWN STATE");
endcase