Wishbone
OpenCores Wishbone — handshakes, burst modes, and lightweight on-chip integration.
Intermediate 1h 40m readOpen-sourceBus
Wishbone is an open-source on-chip interconnect, royalty-free, and widely used in academic and open-source SoCs (OpenCores, RISC-V designs).
What you'll learn
- Wishbone classic vs registered feedback
- Handshake protocol (
stb_o,cyc_o,ack_i) - Block reads/writes
- Comparison with AMBA and how to bridge between them