Structures — Packed & Unpacked

// ── PACKED STRUCT ─────────────────────────────────────────────────
// Fields laid out as contiguous bit vector, MSB-first (first declared = MSB)
typedef struct packed {
logic [3:0]  opcode;   // bits [15:12] — MSB group
logic [3:0]  dst;      // bits [11:8]
logic [3:0]  src;      // bits [7:4]
logic [3:0]  imm;      // bits [3:0]  — LSB group
} instr_t;               // total = 16 bits
 
instr_t      ins;
logic [15:0] raw_bits;
 
// Field access
ins.opcode = 4'hA;
ins.dst    = 4'h3;
ins.src    = 4'h1;
ins.imm    = 4'h7;
 
// Packed struct ↔ logic vector (same total width)
raw_bits = ins;                   // 16'hA317 — direct assignment
ins      = instr_t'(raw_bits);   // logic → packed struct via cast
 
// ── UNPACKED STRUCT ───────────────────────────────────────────────
// Fields have independent storage; any type is allowed
typedef struct {
logic [31:0] addr;
logic [31:0] data;
bit           is_write;
string        label;      // string: only in unpacked struct
int           latency;
} txn_t;
 
txn_t t1, t2;
t1.addr     = 32'hA000;
t1.data     = 32'hCAFE;
t1.is_write = 1'b1;
t1.label    = "WRITE_0";
t1.latency  = 5;
t2 = t1;    // deep copy — t2 is independent of t1
 
// ── STRUCT LITERAL ────────────────────────────────────────────────
instr_t ins2 = '{opcode:4'h5, dst:4'h2, src:4'h1, imm:4'h0};
txn_t   t3   = '{addr:32'h1000, data:32'hFF, is_write:1, label:"RD", latency:3};
// Or positional (order must match declaration):
instr_t ins3 = '{4'h5, 4'h2, 4'h1, 4'h0};  // positional
 
// ── SIGNED PACKED STRUCT ──────────────────────────────────────────
typedef struct packed signed {
logic [15:0] real_part;
logic [15:0] imag_part;
} complex_t;   // whole struct treated as signed 32-bit when used as vector
 
// ── NESTED STRUCT ─────────────────────────────────────────────────
typedef struct packed {
instr_t  cmd;     // nested packed struct
logic    valid;
} pkt_t;   // total = 17 bits
 
pkt_t pkt;
pkt.cmd.opcode = 4'hF;   // nested field access
pkt.valid      = 1'b1;

module tb_packed_struct;
 
// 32-bit control register layout:
// [31:24] = timeout (8 bits)  [23:16] = max_retry (8 bits)
// [15:8]  = mode    (8 bits)  [7:0]   = flags     (8 bits)
typedef struct packed {
logic [7:0] timeout;
logic [7:0] max_retry;
logic [7:0] mode;
logic [7:0] flags;
} ctrl_reg_t;
 
ctrl_reg_t   ctrl;
logic [31:0] raw;
 
initial begin
// ── Field-by-field assignment ─────────────────────────────────
ctrl.timeout   = 8'd100;
ctrl.max_retry = 8'd3;
ctrl.mode      = 8'h05;
ctrl.flags     = 8'b0000_0001;
 
// ── Packed struct → raw bits ──────────────────────────────────
raw = ctrl;
$display("ctrl raw = 0x%08h", raw);   // 0x64030501
$display("timeout  = %0d", ctrl.timeout);    // 100
$display("flags    = %08b", ctrl.flags);     // 00000001
 
// ── Assign raw bits to struct ─────────────────────────────────
raw  = 32'hAABBCCDD;
ctrl = ctrl_reg_t'(raw);
$display("From raw 0xAABBCCDD:");
$display("  timeout   = 0x%02h", ctrl.timeout);    // AA
$display("  max_retry = 0x%02h", ctrl.max_retry);  // BB
$display("  mode      = 0x%02h", ctrl.mode);       // CC
$display("  flags     = 0x%02h", ctrl.flags);      // DD
 
// ── Struct literal ────────────────────────────────────────────
ctrl = '{timeout:8'd50, max_retry:8'd5, mode:8'h02, flags:8'h00};
$display("Literal: 0x%08h", logic'(ctrl));  // 0x32050200
 
$finish;
end
 
endmodule

// AXI4 Write Address Channel beat — pack into single vector for monitoring
typedef struct packed {
logic [7:0]  awid;
logic [31:0] awaddr;
logic [7:0]  awlen;
logic [2:0]  awsize;
logic [1:0]  awburst;
} axi_aw_t;   // total = 56 bits
 
module tb_axi_struct;
 
axi_aw_t aw_beat;
 
// Build a write beat for a 4-beat INCR burst at 0xA000_0000
initial begin
aw_beat = '{
awid:    8'h05,
awaddr:  32'hA000_0000,
awlen:   8'd3,       // 4 beats (len+1)
awsize:  3'b010,     // 4 bytes per beat
awburst: 2'b01       // INCR
};
 
$display("AW Beat:");
$display("  AWID    = 0x%02h", aw_beat.awid);
$display("  AWADDR  = 0x%08h", aw_beat.awaddr);
$display("  AWLEN   = %0d (burst of %0d)", aw_beat.awlen, aw_beat.awlen+1);
$display("  AWBURST = %02b (INCR)", aw_beat.awburst);
 
// Pass the packed struct as a single 56-bit vector
logic [55:0] raw_beat = aw_beat;
$display("Packed: 0x%014h", raw_beat);
 
// Reconstruct from raw bits
axi_aw_t recovered = axi_aw_t'(raw_beat);
$display("Recovered addr: 0x%08h", recovered.awaddr);
 
$finish;
end
 
endmodule

typedef enum logic [1:0] { OKAY, EXOKAY, SLVERR, DECERR } resp_t;
 
typedef struct {
logic [7:0]  tid;
logic [31:0] addr;
logic [31:0] data [];    // dynamic array — ONLY in unpacked struct
resp_t        resp;
string        label;     // string — ONLY in unpacked struct
int           latency;
} axi_resp_txn_t;
 
module tb_unpacked_struct;
 
task automatic print_txn(input axi_resp_txn_t t);
$display("[%s] tid=0x%h addr=0x%08h resp=%s lat=%0d",
t.label, t.tid, t.addr, t.resp.name(), t.latency);
foreach (t.data[i])
$display("  data[%0d] = 0x%08h", i, t.data[i]);
endtask
 
task automatic compare_txn(input axi_resp_txn_t exp, got);
if (exp.tid  !== got.tid)   $error("TID mismatch");
if (exp.addr !== got.addr)  $error("ADDR mismatch");
if (exp.resp !== got.resp)
$error("RESP: exp=%s got=%s", exp.resp.name(), got.resp.name());
foreach (exp.data[i])
if (exp.data[i] !== got.data[i])
$error("data[%0d] mismatch: exp=0x%h got=0x%h", i, exp.data[i], got.data[i]);
$display("PASS: %s", exp.label);
endtask
 
initial begin
axi_resp_txn_t t1, t2;
 
t1.tid     = 8'h07;
t1.addr    = 32'hA000_0100;
t1.data    = new[2]('{32'hAAAA, 32'hBBBB});
t1.resp    = OKAY;
t1.label   = "write_beat_0";
t1.latency = 8;
 
print_txn(t1);
 
t2 = t1;             // whole-struct copy — t2 is independent
t2.data[0] = 32'hCCCC;  // does NOT affect t1.data[0]
compare_txn(t1, t2); // will report data[0] mismatch
 
$finish;
end
 
endmodule

package axi_pkg;
typedef struct packed {
logic         awvalid;
logic [31:0]  awaddr;
logic [7:0]   awlen;
logic [1:0]   awburst;
} axi_aw_t;   // 42 bits total
endpackage
 
import axi_pkg::*;
 
// DUT: receives packed struct on a single port
module axi_slave (
input  logic   clk,
input  axi_aw_t aw,       // packed struct port — one 42-bit input
output logic   awready
);
assign awready = aw.awvalid;   // access fields directly
endmodule
 
// Testbench: drive the packed struct port
module tb_port_struct;
import axi_pkg::*;
 
logic   clk = 0;
axi_aw_t aw_drive;
logic   awready;
 
axi_slave dut (.clk(clk), .aw(aw_drive), .awready(awready));
always #5 clk = ~clk;
 
initial begin
aw_drive = '{awvalid:1'b0, awaddr:32'h0, awlen:8'h0, awburst:2'b00};
@(posedge clk);
aw_drive.awvalid = 1'b1;
aw_drive.awaddr  = 32'hA000_0000;
aw_drive.awlen   = 8'd15;
aw_drive.awburst = 2'b01;
@(posedge clk);
$display("awready = %0b", awready);   // 1
$finish;
end
endmodule

// ── 1. PACKED STRUCT FOR REGISTER MAP FIELD ACCESS ────────────────
typedef struct packed {
logic         err_en;    // [31]
logic [6:0]   rsvd;      // [30:24]
logic [7:0]   timeout;   // [23:16]
logic [15:0]  base_addr; // [15:0]
} dma_ctrl_t;
 
dma_ctrl_t   ctrl_shadow;   // mirror of DUT register
logic [31:0] reg_readback;
 
// After reading DUT register via RAL:
ctrl_shadow = dma_ctrl_t'(reg_readback);
$display("err_en=%b timeout=%0d base=0x%04h",
ctrl_shadow.err_en, ctrl_shadow.timeout, ctrl_shadow.base_addr);
 
// ── 2. UNPACKED STRUCT FOR TRANSACTION QUEUES ─────────────────────
typedef struct {
logic [7:0]  tid;
logic [31:0] addr;
logic [31:0] data;
bit           is_write;
} beat_t;
 
beat_t exp_q [$];   // queue of struct objects
beat_t got_q [$];
 
// ── 3. PACKED STRUCT COMPARISON (uses === for X detection) ────────
function automatic bit beats_match(input beat_t e, g);
return (e.tid === g.tid && e.addr === g.addr && e.data === g.data);
endfunction
 
// ── 4. STRUCT IN COVERAGE ─────────────────────────────────────────
// covergroup cg_beat with function sample(beat_t b);
//   cp_rw:   coverpoint b.is_write;
//   cp_addr: coverpoint b.addr[31:28]; // top nibble
// endgroup
 
// ── 5. NESTED PACKED STRUCT FOR AXI W BEAT ────────────────────────
typedef struct packed {
logic [7:0]  wstrb;
logic [31:0] wdata;
logic         wlast;
} axi_w_beat_t;   // 41 bits total — directly connectable to AXI W channel

// Register spec: [31:24]=opcode, [23:16]=addr_hi, [15:0]=addr_lo
 
// BUGGY: fields declared in wrong order (LSB first)
typedef struct packed {
logic [15:0] addr_lo;  // declared first → goes into bits [31:16] — WRONG!
logic [7:0]  addr_hi;  // bits [15:8] — WRONG!
logic [7:0]  opcode;   // bits [7:0] — WRONG!
} bad_reg_t;
 
bad_reg_t r = bad_reg_t'(32'hABCDEF12);
$display("opcode = 0x%02h", r.opcode);    // 12 — WRONG, should be AB
 
// CORRECT: MSB field declared first
typedef struct packed {
logic [7:0]  opcode;   // bits [31:24] — MSB first
logic [7:0]  addr_hi;  // bits [23:16]
logic [15:0] addr_lo;  // bits [15:0]
} good_reg_t;
 
good_reg_t g = good_reg_t'(32'hABCDEF12);
$display("opcode = 0x%02h", g.opcode);    // AB — correct

// BUGGY: dynamic array and string inside packed struct
typedef struct packed {
logic [7:0] tid;
logic [31:0] data [];   // COMPILE ERROR: dynamic array not allowed in packed struct
string       label;     // COMPILE ERROR: string not allowed in packed struct
} bad_t;
 
// FIXED option 1: use unpacked struct for variable-content data
typedef struct {
logic [7:0]  tid;
logic [31:0] data [];   // OK in unpacked
string        label;    // OK in unpacked
} good_t;
 
// FIXED option 2: if you need packed + variable data, use separate fields
typedef struct packed { logic [7:0] tid; logic [31:0] ctrl; } packed_part_t;
typedef struct {
packed_part_t  hdr;       // packed sub-struct
logic [31:0]  payload [];  // dynamic part in unpacked wrapper
} hybrid_t;

typedef struct {   // UNPACKED — note: no 'packed' keyword
logic [31:0] addr;
logic [31:0] data;
} txn_t;
 
// BUGGY: unpacked struct on a module port
module bad_module (input txn_t txn);  // ERROR: port type must be packed
endmodule
 
// FIXED: use packed struct for port connections
typedef struct packed {
logic [31:0] addr;
logic [31:0] data;
} packed_txn_t;
 
module good_module (input packed_txn_t txn);  // OK
$display("addr = 0x%08h", txn.addr);
endmodule