Inside Operator

// General syntax
// result = expression inside { member_list };
// result is 1-bit: 1 = match found, 0 = no match
 
logic [7:0] val;
 
// ── Single values ────────────────────────────────────────────────
val inside {8'h00, 8'hFF}           // 1 if val == 0 or val == 255
 
// ── Range [lo:hi] — closed, inclusive ────────────────────────────
val inside {[8'h10:8'h1F]}           // 1 if 0x10 ≤ val ≤ 0x1F
 
// ── Mixed: values + ranges ────────────────────────────────────────
val inside {8'h00, [8'h10:8'h1F], 8'hFF}
 
// ── Array membership ──────────────────────────────────────────────
logic [7:0] legal_ops[4] = '{8'h10, 8'h20, 8'h30, 8'h40};
val inside {legal_ops}                // tests val against all 4 elements
 
// ── Negation: NOT inside ──────────────────────────────────────────
!(val inside {[8'h10:8'h1F]})         // 1 if val is outside the range
 
// ── In an if statement ────────────────────────────────────────────
if (opcode inside {8'h10, 8'h20, 8'h30})
$display("Legal opcode");
 
// ── In an assign (procedural equivalent) ─────────────────────────
logic is_legal;
assign is_legal = val inside {[8'h00:8'h0F], [8'hF0:8'hFF]};
 
// ── In a constraint block ─────────────────────────────────────────
// constraint legal_addr { addr inside {[32'h0000:32'h0FFF],
//                                      [32'hF000:32'hFFFF]}; }
 
// ── In an SVA assertion ───────────────────────────────────────────
// assert property (@(posedge clk)
//   cmd_valid |-> cmd_opcode inside {4'h1, 4'h2, 4'h4, 4'h8});

module tb_inside_basic;
 
logic [7:0] val;
 
initial begin
 
// ── Single values ─────────────────────────────────────────────
val = 8'hFF;
$display("FF in {00,FF}   = %0b", val inside {8'h00, 8'hFF});    // 1
val = 8'hAB;
$display("AB in {00,FF}   = %0b", val inside {8'h00, 8'hFF});    // 0
 
// ── Range ─────────────────────────────────────────────────────
val = 8'h12;
$display("12 in [10:1F]   = %0b", val inside {[8'h10:8'h1F]});    // 1
val = 8'h20;
$display("20 in [10:1F]   = %0b", val inside {[8'h10:8'h1F]});    // 0
 
// ── Mixed set ─────────────────────────────────────────────────
val = 8'h30;
$display("30 in {00,[10:1F],30,FF} = %0b",
val inside {8'h00, [8'h10:8'h1F], 8'h30, 8'hFF});    // 1
val = 8'h31;
$display("31 in {00,[10:1F],30,FF} = %0b",
val inside {8'h00, [8'h10:8'h1F], 8'h30, 8'hFF});    // 0
 
// ── Negation ──────────────────────────────────────────────────
val = 8'h50;
$display("50 NOT in [10:1F] = %0b", !(val inside {[8'h10:8'h1F]})); // 1
 
// ── Array membership ──────────────────────────────────────────
logic [7:0] opcodes[3] = '{8'h10, 8'h20, 8'h30};
val = 8'h20;
$display("20 in opcodes[] = %0b", val inside {opcodes});           // 1
val = 8'h40;
$display("40 in opcodes[] = %0b", val inside {opcodes});           // 0
 
$finish;
end
 
endmodule

FF in {00,FF}   = 1
AB in {00,FF}   = 0
12 in [10:1F]   = 1
20 in [10:1F]   = 0
30 in {00,[10:1F],30,FF} = 1
31 in {00,[10:1F],30,FF} = 0
50 NOT in [10:1F] = 1
20 in opcodes[] = 1
40 in opcodes[] = 0

// Instruction set: opcodes are grouped by class
// ALU ops:    8'h10 – 8'h1F
// Load/Store: 8'h20 – 8'h2F
// Branch:     8'h30, 8'h31, 8'h32
// NOP:        8'h00
 
module tb_opcode_decoder;
 
logic [7:0] opcode;
 
function automatic void decode(input logic [7:0] op);
if      (op inside {[8'h10:8'h1F]})              $display("0x%02h → ALU operation",   op);
else if (op inside {[8'h20:8'h2F]})              $display("0x%02h → Load/Store",      op);
else if (op inside {8'h30, 8'h31, 8'h32})       $display("0x%02h → Branch",          op);
else if (op == 8'h00)                            $display("0x%02h → NOP",            op);
else                                              $display("0x%02h → ILLEGAL opcode",  op);
endfunction
 
initial begin
decode(8'h00);   // NOP
decode(8'h15);   // ALU
decode(8'h1F);   // ALU (hi bound)
decode(8'h20);   // Load/Store (lo bound)
decode(8'h31);   // Branch
decode(8'hAB);   // ILLEGAL
$finish;
end
 
endmodule

0x00 → NOP
0x15 → ALU operation
0x1F → ALU operation
0x20 → Load/Store
0x31 → Branch
0xAB → ILLEGAL opcode

// AXI transaction: constrain address to valid memory map regions
 
class axi_transaction;
 
rand logic [31:0] addr;
rand logic [7:0]  burst_len;
rand logic [1:0]  burst_type;
 
// Only generate addresses within valid memory map regions
constraint valid_addr {
addr inside {
[32'h0000_0000:32'h0000_FFFF],   // BOOT ROM
[32'h1000_0000:32'h1FFF_FFFF],   // SRAM
[32'hC000_0000:32'hCFFF_FFFF]    // Peripheral APB
};
}
 
// Burst length: short (1-4) or page-aligned (8, 16)
constraint valid_burst {
burst_len inside {[8'd1:8'd4], 8'd8, 8'd16};
}
 
// Burst type: FIXED or INCR only (not WRAP for this test)
constraint burst_type_c {
burst_type inside {2'b00, 2'b01};    // FIXED=00, INCR=01
}
 
// Scoreboard checker: validate received transaction
function void check_legal();
if (!(addr inside {[32'h0000_0000:32'h0000_FFFF],
[32'h1000_0000:32'h1FFF_FFFF],
[32'hC000_0000:32'hCFFF_FFFF]}))
$error("ILLEGAL addr = 0x%08h", addr);
if (!(burst_len inside {[8'd1:8'd4], 8'd8, 8'd16}))
$error("ILLEGAL burst_len = %0d", burst_len);
endfunction
 
endclass
 
module tb_constraint_inside;
initial begin
axi_transaction txn = new();
repeat(5) begin
void'(txn.randomize());
$display("addr=0x%08h burst_len=%0d burst_type=%02b",
txn.addr, txn.burst_len, txn.burst_type);
txn.check_legal();
end
$finish;
end
endmodule

module tb_inside_xz;
 
logic [3:0] val;
 
initial begin
 
// ── Wildcard member: X bits are don't-cares ────────────────────
// 4'b1X1X matches any value where bit3=1 and bit1=1
val = 4'b1010;
$display("1010 inside {1X1X} = %0b", val inside {4'b1X1X});  // 1
val = 4'b1110;
$display("1110 inside {1X1X} = %0b", val inside {4'b1X1X});  // 1
val = 4'b0010;
$display("0010 inside {1X1X} = %0b", val inside {4'b1X1X});  // 0 (bit3=0)
val = 4'b1001;
$display("1001 inside {1X1X} = %0b", val inside {4'b1X1X});  // 0 (bit1=0)
 
// ── X in the tested value ─────────────────────────────────────
val = 4'bXX10;
$display("XX10 inside {1X1X} = %0b", val inside {4'b1X1X});  // X (bit3 unknown)
 
// ── Clean value, wildcard member covers all possibilities ─────
// 4'bXXXX as a member matches EVERYTHING — acts as a wildcard
val = 4'hA;
$display("0xA inside {XXXX}  = %0b", val inside {4'bXXXX});   // 1
 
// ── Range endpoint with X: undefined behavior — avoid ─────────
// inside {[4'bXX00:4'b1111]} — bounds contain X, result is X
// Best practice: always use clean (non-X) range bounds
 
$finish;
end
 
endmodule

1010 inside {1X1X} = 1
1110 inside {1X1X} = 1
0010 inside {1X1X} = 0
1001 inside {1X1X} = 0
XX10 inside {1X1X} = x
0xA inside {XXXX}  = 1

// ── 1. CONSTRAINT: address alignment + region filter ─────────────
constraint addr_map {
addr inside {[32'h0000_0000:32'h0FFF_FFFF],  // DDR
[32'hA000_0000:32'hA000_FFFF]};  // MMIO
addr[1:0] == 2'b00;    // 4-byte aligned
}
 
// ── 2. SCOREBOARD: validate DUT response code ─────────────────────
function void check_resp(input logic [1:0] resp);
if (!(resp inside {2'b00, 2'b01}))   // OKAY or EXOKAY only
$error("Unexpected AXI response: %02b", resp);
endfunction
 
// ── 3. SVA ASSERTION: legal state transitions ─────────────────────
// assert property (@(posedge clk) disable iff (rst)
//   state_valid |-> next_state inside {ST_IDLE, ST_ACTIVE, ST_DRAIN});
 
// ── 4. COVERAGE: conditional sample based on membership ───────────
// covergroup cg_burst;
//   cp_len: coverpoint burst_len {
//     bins short  = {[1:4]};
//     bins medium = {[5:15]};
//     bins long   = {[16:255]};
//   }
// endgroup
 
// ── 5. DRIVER: select stimulus type based on address region ───────
function string get_region(input logic [31:0] a);
if      (a inside {[32'h0000_0000:32'h0FFF_FFFF]}) return "DDR";
else if (a inside {[32'hA000_0000:32'hAFFF_FFFF]}) return "MMIO";
else                                                return "UNMAPPED";
endfunction
 
// ── 6. PROTOCOL CHECKER: illegal burst type for region ────────────
// AXI rule: WRAP bursts only allowed in cacheable region
if (burst_type == 2'b10 && !(addr inside {[32'h1000_0000:32'h1FFF_FFFF]}))
$error("WRAP burst to non-cacheable address 0x%08h", addr);

logic [7:0] val = 8'h15;
 
// BUGGY: lo > hi — the range [8'h1F:8'h10] is empty in most tools
// No value can satisfy hi ≥ val ≥ lo when lo > hi
if (val inside {[8'h1F:8'h10]})   // silently returns 0 always
$display("Inside");
// Waveform: 'Inside' never prints, even for val=8'h15
 
// FIXED: low bound first
if (val inside {[8'h10:8'h1F]})   // correct: [lo:hi]
$display("Inside");              // now prints for 0x15

logic signed [7:0] sval = -1;   // 8'hFF in two's complement
 
// Engineer expects: -1 is NOT inside [0:127]
// But the range bounds 0 and 127 are treated as unsigned in inside{}
// -1 = 8'hFF = 255 unsigned
// 255 is NOT in [0:127] → result is 0 — happens to be correct here
if (sval inside {[8'sh00:8'sh7F]})
$display("In positive range");
 
// TRAP: what about -1 inside [-128:0] (negative range)?
// -128 = 8'b1000_0000 = 8'h80 unsigned (128)
// -1   = 8'b1111_1111 = 8'hFF unsigned (255)
// Range [8'sh80:8'sh00] interpreted as [128:0] unsigned — EMPTY! (128 > 0)
if (sval inside {[8'sh80:8'sh00]})   // BUGGY: empty range
$display("In negative range");       // never prints!
 
// CORRECT: for signed ranges, ensure comparison context is signed
// Use explicit comparisons when mixing signed values with inside ranges
if ($signed(sval) >= -128 && $signed(sval) <= -1)
$display("Negative value confirmed");   // correct approach for signed

// In a CONSTRAINT block, inside uses == (exact equality, no wildcard)
// In PROCEDURAL code, inside uses ==? (wildcard equality)
// This is a subtle but important difference
 
class pkt;
rand logic [3:0] val;
// In constraint: inside uses == — X in member is NOT a don't-care
// Writing {4'b1X10} in a constraint means the literal value with X bits
// The solver cannot randomize to X/Z, so this effectively matches nothing
constraint bad_c { val inside {4'b1X10}; }  // ISSUE: no valid 2-state value matches
endclass
 
// Procedural context — X member IS a wildcard
logic [3:0] check_val = 4'b1010;
$display("proc: 1010 inside {1X10} = %0b",
check_val inside {4'b1X10});  // 1 — wildcard: bit2=X is don't-care
 
// CORRECT for constraint: list all explicit values or use a range
class pkt_fixed;
rand logic [3:0] val;
// Want: all 4-bit values where bit3=1 and bit1=1 (i.e., 4'b1X1X pattern)
// Enumerate them explicitly: 1010, 1011, 1110, 1111
constraint good_c { val inside {4'b1010, 4'b1011, 4'b1110, 4'b1111}; }
endclass

// BUGGY: using inside in an assign — synthesis may fail or warn
module decoder (
input  logic [7:0] opcode,
output logic        is_alu
);
// May synthesize with Synopsys DC 2019+ but not older tools
assign is_alu = opcode inside {[8'h10:8'h1F]};   // RISKY
 
endmodule
 
// CORRECT: expand to explicit comparison — portable across all tools
module decoder_safe (
input  logic [7:0] opcode,
output logic        is_alu
);
assign is_alu = (opcode >= 8'h10) && (opcode <= 8'h1F);  // always synthesizable
 
endmodule

class bad_txn;
rand logic [7:0] burst_len;
 
// Constraint A: burst length in {1,2,3,4,8,16}
constraint len_set  { burst_len inside {[8'd1:8'd4], 8'd8, 8'd16}; }
 
// Constraint B: burst length must be > 16 (added later, contradicts A)
constraint len_min  { burst_len > 16; }
// randomize() will FAIL — no value satisfies both constraints
// $error: "Randomization failed"
endclass
 
module tb_constraint_debug;
initial begin
bad_txn t = new();
if (!t.randomize())
$error("Randomize failed — check for constraint contradiction");
 
// DEBUG: disable one constraint to isolate the conflict
t.randomize() with { burst_len inside {[8'd1:8'd4]}; };
// Works → confirms len_min was the conflicting constraint
$finish;
end
endmodule